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git01.mediatek.com / filogic / uboot / 4078fec1ee6a908821051e849763ac63d0e9c62a / . / arch / powerpc / cpu / mpc85xx / p5040_serdes.c
blob: 2327b2c2a414339d2adf43f068dd954c3ef2de2b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]2/*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]4 */
5
6#include <common.h>
7#include <asm/fsl_serdes.h>
8#include <asm/processor.h>
9#include <asm/io.h>
10#include "fsl_corenet_serdes.h"
11
12/*
13 * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame]14 * U-Boot only supports one SerDes controller. Therefore, we ignore bank 4 in
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]15 * this table. This works because most of the SerDes code is for errata
16 * work-arounds, and there are no P5040 errata that effect bank 4.
17 */
18
19static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
20 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
21 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
22 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
23 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
24 [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
25 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
26 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
27 XAUI_FM2, /* SATA1, SATA2 */ },
28 [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
29 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
30 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
31 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
32 [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
33 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
34 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
35 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
36 /* SATA1, SATA2 */ },
37 [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
38 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
39 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
40 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
41 /* SATA1, SATA2 */ },
42 [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
43 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
44 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
45 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
46 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
47 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
48 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
49 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
50 [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
51 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
52 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
53 XAUI_FM2, /* SATA1, SATA2 */ },
54 [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
55 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
56 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
57 /* NONE, NONE */ },
58 [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
59 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
60 NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
61 [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
62 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
63 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
64 XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
65 [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
66 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
67 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
68 NONE, SATA1, SATA2, /* NONE, NONE */ },
69 [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
70 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
71 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
72 /* NONE, NONE */ },
73 [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
74 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
75 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
76 NONE, SATA1, SATA2, /* NONE, NONE */ },
77};
78
79enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
80{
81 if (!serdes_lane_enabled(lane))
82 return NONE;
83
84 return serdes_cfg_tbl[cfg][lane];
85}
86
87int is_serdes_prtcl_valid(u32 prtcl)
88{
89 int i;
90
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]91 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]92 return 0;
93
94 for (i = 0; i < SRDS_MAX_LANES; i++) {
95 if (serdes_cfg_tbl[prtcl][i] != NONE)
96 return 1;
97 }
98
99 return 0;
100}