blob: c78def5066ed34a2c28c83e49c91f8620626914f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasutbcd861b2016-11-16 17:20:23 +01002/*
3 * Specialty padding for the Altera SoCFPGA preloader image
Marek Vasutbcd861b2016-11-16 17:20:23 +01004 */
5
6#ifndef __BOOT0_H
7#define __BOOT0_H
8
Philipp Tomsich85bd93d2017-10-10 16:21:07 +02009_start:
10 ARM_VECTORS
11
Marek Vasutbcd861b2016-11-16 17:20:23 +010012#ifdef CONFIG_SPL_BUILD
Chee, Tien Fong19869ea2017-03-29 11:49:16 +080013 .balignl 64,0xf33db33f;
14
15 .word 0x1337c0d3; /* SoCFPGA preloader validation word */
16 .word 0xc01df00d; /* Version, flags, length */
17 .word 0xcafec0d3; /* Checksum, zero-pad */
Marek Vasutbcd861b2016-11-16 17:20:23 +010018 nop;
Marek Vasutbcd861b2016-11-16 17:20:23 +010019
Marek Vasut323f9de2018-04-15 13:15:33 +020020 b reset; /* SoCFPGA Gen5 jumps here */
21 b reset; /* SoCFPGA Gen10 trampoline */
Chee, Tien Fong19869ea2017-03-29 11:49:16 +080022 nop;
23 nop;
24#endif
Marek Vasutbcd861b2016-11-16 17:20:23 +010025
26#endif /* __BOOT0_H */