wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 1 | /* |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 2 | * (C) Copyright 2003-2004 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 4 | * |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 5 | * (C) Copyright 2004 |
| 6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
| 7 | * |
| 8 | * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn |
| 9 | * garyj@denx.de |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 10 | * |
| 11 | * See file CREDITS for list of people who contributed to this |
| 12 | * project. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License as |
| 16 | * published by the Free Software Foundation; either version 2 of |
| 17 | * the License, or (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 27 | * MA 02111-1307 USA |
| 28 | */ |
| 29 | |
| 30 | #include <common.h> |
| 31 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 32 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 33 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 34 | /* |
| 35 | * CPU to flash interface is 32-bit, so make declaration accordingly |
| 36 | */ |
| 37 | typedef unsigned short FLASH_PORT_WIDTH; |
| 38 | typedef volatile unsigned short FLASH_PORT_WIDTHV; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 39 | |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 40 | #define FPW FLASH_PORT_WIDTH |
| 41 | #define FPWV FLASH_PORT_WIDTHV |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 42 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 43 | #define FLASH_CYCLE1 0x0555 |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 44 | #define FLASH_CYCLE2 0x02AA |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 45 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 46 | /*----------------------------------------------------------------------- |
| 47 | * Functions |
| 48 | */ |
| 49 | static ulong flash_get_size(FPWV *addr, flash_info_t *info); |
| 50 | static void flash_reset(flash_info_t *info); |
| 51 | static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); |
| 52 | static flash_info_t *flash_get_info(ulong base); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 53 | |
| 54 | /*----------------------------------------------------------------------- |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 55 | * flash_init() |
| 56 | * |
| 57 | * sets up flash_info and returns size of FLASH (bytes) |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 58 | */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 59 | unsigned long flash_init (void) |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 60 | { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 61 | unsigned long size = 0; |
| 62 | ulong flashbase = CFG_FLASH_BASE; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 63 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 64 | /* Init: no FLASHes known */ |
| 65 | memset(&flash_info[0], 0, sizeof(flash_info_t)); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 66 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 67 | flash_info[0].size = |
| 68 | flash_get_size((FPW *)flashbase, &flash_info[0]); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 69 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 70 | size = flash_info[0].size; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 71 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 72 | #if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
| 73 | /* monitor protection ON by default */ |
| 74 | flash_protect(FLAG_PROTECT_SET, |
| 75 | CFG_MONITOR_BASE, |
| 76 | CFG_MONITOR_BASE+monitor_flash_len-1, |
| 77 | flash_get_info(CFG_MONITOR_BASE)); |
| 78 | #endif |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 79 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 80 | #ifdef CFG_ENV_IS_IN_FLASH |
| 81 | /* ENV protection ON by default */ |
| 82 | flash_protect(FLAG_PROTECT_SET, |
| 83 | CFG_ENV_ADDR, |
| 84 | CFG_ENV_ADDR+CFG_ENV_SIZE-1, |
| 85 | flash_get_info(CFG_ENV_ADDR)); |
| 86 | #endif |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 87 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 88 | return size ? size : 1; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 89 | } |
| 90 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 91 | /*----------------------------------------------------------------------- |
| 92 | */ |
| 93 | static void flash_reset(flash_info_t *info) |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 94 | { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 95 | FPWV *base = (FPWV *)(info->start[0]); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 96 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 97 | /* Put FLASH back in read mode */ |
| 98 | if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 99 | *base = (FPW)0x00FF; /* Intel Read Mode */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 100 | else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 101 | *base = (FPW)0x00F0; /* AMD Read Mode */ |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 102 | } |
| 103 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 104 | /*----------------------------------------------------------------------- |
| 105 | */ |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 106 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 107 | static flash_info_t *flash_get_info(ulong base) |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 108 | { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 109 | int i; |
| 110 | flash_info_t * info; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 111 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 112 | info = NULL; |
| 113 | for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { |
| 114 | info = & flash_info[i]; |
| 115 | if (info->size && info->start[0] <= base && |
| 116 | base <= info->start[0] + info->size - 1) |
| 117 | break; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 118 | } |
| 119 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 120 | return i == CFG_MAX_FLASH_BANKS ? 0 : info; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /*----------------------------------------------------------------------- |
| 124 | */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 125 | |
| 126 | void flash_print_info (flash_info_t *info) |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 127 | { |
| 128 | int i; |
| 129 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 130 | if (info->flash_id == FLASH_UNKNOWN) { |
| 131 | printf ("missing or unknown FLASH type\n"); |
| 132 | return; |
| 133 | } |
| 134 | |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 135 | switch (info->flash_id & FLASH_VENDMASK) { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 136 | case FLASH_MAN_AMD: printf ("AMD "); break; |
| 137 | case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; |
| 138 | case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
| 139 | case FLASH_MAN_SST: printf ("SST "); break; |
| 140 | case FLASH_MAN_STM: printf ("STM "); break; |
| 141 | case FLASH_MAN_INTEL: printf ("INTEL "); break; |
| 142 | default: printf ("Unknown Vendor "); break; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | switch (info->flash_id & FLASH_TYPEMASK) { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 146 | case FLASH_S29GL064M: |
| 147 | printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n"); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 148 | break; |
| 149 | default: |
| 150 | printf ("Unknown Chip Type\n"); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 151 | break; |
| 152 | } |
| 153 | |
| 154 | printf (" Size: %ld MB in %d Sectors\n", |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 155 | info->size >> 20, |
| 156 | info->sector_count); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 157 | |
| 158 | printf (" Sector Start Addresses:"); |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 159 | |
| 160 | for (i=0; i<info->sector_count; ++i) { |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 161 | if ((i % 5) == 0) { |
| 162 | printf ("\n "); |
| 163 | } |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 164 | printf (" %08lX%s", |
| 165 | info->start[i], |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 166 | info->protect[i] ? " (RO)" : " "); |
| 167 | } |
| 168 | printf ("\n"); |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 169 | return; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /*----------------------------------------------------------------------- |
| 173 | */ |
| 174 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 175 | /* |
| 176 | * The following code cannot be run from FLASH! |
| 177 | */ |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 178 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 179 | ulong flash_get_size (FPWV *addr, flash_info_t *info) |
| 180 | { |
| 181 | int i; |
| 182 | ulong base = (ulong)addr; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 183 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 184 | /* Write auto select command: read Manufacturer ID */ |
| 185 | /* Write auto select command sequence and test FLASH answer */ |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 186 | addr[FLASH_CYCLE1] = (FPW)0x00AA; /* for AMD, Intel ignores this */ |
| 187 | addr[FLASH_CYCLE2] = (FPW)0x0055; /* for AMD, Intel ignores this */ |
| 188 | addr[FLASH_CYCLE1] = (FPW)0x0090; /* selects Intel or AMD */ |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 189 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 190 | /* The manufacturer codes are only 1 byte, so just use 1 byte. |
| 191 | * This works for any bus width and any FLASH device width. |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 192 | */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 193 | udelay(100); |
| 194 | switch (addr[0] & 0xff) { |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 195 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 196 | case (uchar)AMD_MANUFACT: |
| 197 | printf ("Manufacturer: AMD (Spansion)\n"); |
| 198 | info->flash_id = FLASH_MAN_AMD; |
| 199 | break; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 200 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 201 | case (uchar)INTEL_MANUFACT: |
| 202 | printf ("Manufacturer: Intel (not supported yet)\n"); |
| 203 | info->flash_id = FLASH_MAN_INTEL; |
| 204 | break; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 205 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 206 | default: |
| 207 | info->flash_id = FLASH_UNKNOWN; |
| 208 | info->sector_count = 0; |
| 209 | info->size = 0; |
| 210 | break; |
| 211 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 212 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 213 | /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ |
| 214 | if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 215 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 216 | case AMD_ID_MIRROR: |
| 217 | printf ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n", |
| 218 | addr[14], addr[15]); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 219 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 220 | switch(addr[14] & 0xffff) { |
| 221 | case (AMD_ID_GL064M_2 & 0xffff): |
| 222 | if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) { |
| 223 | printf ("Chip: S29GLxxxM -> unknown\n"); |
| 224 | info->flash_id = FLASH_UNKNOWN; |
| 225 | info->sector_count = 0; |
| 226 | info->size = 0; |
| 227 | } else { |
| 228 | printf ("Chip: S29GL064M-R6\n"); |
| 229 | info->flash_id += FLASH_S29GL064M; |
| 230 | info->sector_count = 128; |
| 231 | info->size = 0x00800000; |
| 232 | for (i = 0; i < info->sector_count; i++) { |
| 233 | info->start[i] = base; |
| 234 | base += 0x10000; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 235 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 236 | } |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 237 | break; /* => 16 MB */ |
| 238 | default: |
| 239 | printf ("Chip: *** unknown ***\n"); |
| 240 | info->flash_id = FLASH_UNKNOWN; |
| 241 | info->sector_count = 0; |
| 242 | info->size = 0; |
| 243 | break; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 244 | } |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 245 | break; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 246 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 247 | default: |
| 248 | info->flash_id = FLASH_UNKNOWN; |
| 249 | info->sector_count = 0; |
| 250 | info->size = 0; |
| 251 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 252 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 253 | /* Put FLASH back in read mode */ |
| 254 | flash_reset(info); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 255 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 256 | return (info->size); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | /*----------------------------------------------------------------------- |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 260 | */ |
| 261 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 262 | int flash_erase (flash_info_t *info, int s_first, int s_last) |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 263 | { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 264 | FPWV *addr = (FPWV *)(info->start[0]); |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 265 | int flag, prot, sect, ssect, l_sect; |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 266 | ulong start, now, last; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 267 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 268 | printf ("flash_erase: first: %d last: %d\n", s_first, s_last); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 269 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 270 | if ((s_first < 0) || (s_first > s_last)) { |
| 271 | if (info->flash_id == FLASH_UNKNOWN) { |
| 272 | printf ("- missing\n"); |
| 273 | } else { |
| 274 | printf ("- no sectors to erase\n"); |
| 275 | } |
| 276 | return 1; |
| 277 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 278 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 279 | if ((info->flash_id == FLASH_UNKNOWN) || |
| 280 | (info->flash_id > FLASH_AMD_COMP)) { |
| 281 | printf ("Can't erase unknown flash type %08lx - aborted\n", |
| 282 | info->flash_id); |
| 283 | return 1; |
| 284 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 285 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 286 | prot = 0; |
| 287 | for (sect=s_first; sect<=s_last; ++sect) { |
| 288 | if (info->protect[sect]) { |
| 289 | prot++; |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | if (prot) { |
| 294 | printf ("- Warning: %d protected sectors will not be erased!\n", |
| 295 | prot); |
| 296 | } else { |
| 297 | printf ("\n"); |
| 298 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 299 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 300 | /* Disable interrupts which might cause a timeout here */ |
| 301 | flag = disable_interrupts(); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 302 | |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 303 | /* |
| 304 | * Start erase on unprotected sectors. |
| 305 | * Since the flash can erase multiple sectors with one command |
| 306 | * we take advantage of that by doing the erase in chunks of |
| 307 | * 3 sectors. |
| 308 | */ |
| 309 | for (sect = s_first; sect <= s_last; ) { |
| 310 | l_sect = -1; |
| 311 | |
| 312 | addr[FLASH_CYCLE1] = 0x00AA; |
| 313 | addr[FLASH_CYCLE2] = 0x0055; |
| 314 | addr[FLASH_CYCLE1] = 0x0080; |
| 315 | addr[FLASH_CYCLE1] = 0x00AA; |
| 316 | addr[FLASH_CYCLE2] = 0x0055; |
| 317 | |
| 318 | /* do the erase in chunks of at most 3 sectors */ |
| 319 | for (ssect = 0; ssect < 3; ssect++) { |
| 320 | if ((sect + ssect) > s_last) |
| 321 | break; |
| 322 | if (info->protect[sect + ssect] == 0) { /* not protected */ |
| 323 | addr = (FPWV *)(info->start[sect + ssect]); |
| 324 | addr[0] = 0x0030; |
| 325 | l_sect = sect + ssect; |
| 326 | } |
| 327 | } |
| 328 | /* wait at least 80us - let's wait 1 ms */ |
| 329 | udelay (1000); |
| 330 | |
| 331 | /* |
| 332 | * We wait for the last triggered sector |
| 333 | */ |
| 334 | if (l_sect < 0) |
| 335 | goto DONE; |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 336 | |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 337 | start = get_timer (0); |
| 338 | last = start; |
| 339 | addr = (FPWV *)(info->start[l_sect]); |
| 340 | while ((addr[0] & 0x0080) != 0x0080) { |
| 341 | if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
| 342 | printf ("Timeout\n"); |
| 343 | return 1; |
| 344 | } |
| 345 | /* show that we're waiting */ |
| 346 | if ((now - last) > 1000) { /* every second */ |
| 347 | putc ('.'); |
| 348 | last = now; |
| 349 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 350 | } |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 351 | addr = (FPWV *)info->start[0]; |
| 352 | addr[0] = 0x00F0; /* reset bank */ |
| 353 | sect += ssect; |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 354 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 355 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 356 | /* re-enable interrupts if necessary */ |
| 357 | if (flag) |
| 358 | enable_interrupts(); |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 359 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 360 | DONE: |
| 361 | /* reset to read mode */ |
| 362 | addr = (FPWV *)info->start[0]; |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 363 | addr[0] = 0x00F0; /* reset bank */ |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 364 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 365 | printf (" done\n"); |
| 366 | return 0; |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 367 | } |
| 368 | |
| 369 | /*----------------------------------------------------------------------- |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 370 | * Copy memory to flash, returns: |
| 371 | * 0 - OK |
| 372 | * 1 - write timeout |
| 373 | * 2 - Flash not erased |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 374 | */ |
| 375 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 376 | int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 377 | { |
| 378 | ulong wp, data; |
| 379 | int rc; |
| 380 | |
| 381 | if (addr & 1) { |
| 382 | printf ("unaligned destination not supported\n"); |
| 383 | return ERR_ALIGN; |
| 384 | }; |
| 385 | |
| 386 | if ((int) src & 1) { |
| 387 | printf ("unaligned source not supported\n"); |
| 388 | return ERR_ALIGN; |
| 389 | }; |
| 390 | |
| 391 | wp = addr; |
| 392 | |
| 393 | while (cnt >= 2) { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 394 | data = *((FPWV *)src); |
| 395 | if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 396 | return (rc); |
| 397 | } |
| 398 | src += 2; |
| 399 | wp += 2; |
| 400 | cnt -= 2; |
| 401 | } |
| 402 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 403 | if (cnt == 0) { |
| 404 | return (0); |
| 405 | } |
| 406 | |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 407 | if (cnt == 1) { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 408 | data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) |
| 409 | << 8); |
| 410 | if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 411 | return (rc); |
| 412 | } |
| 413 | src += 1; |
| 414 | wp += 1; |
| 415 | cnt -= 1; |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 416 | } |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 417 | |
| 418 | return ERR_OK; |
| 419 | } |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 420 | |
| 421 | /*----------------------------------------------------------------------- |
| 422 | * Write a word to Flash for AMD FLASH |
| 423 | * A word is 16 or 32 bits, whichever the bus width of the flash bank |
| 424 | * (not an individual chip) is. |
| 425 | * |
| 426 | * returns: |
| 427 | * 0 - OK |
| 428 | * 1 - write timeout |
| 429 | * 2 - Flash not erased |
| 430 | */ |
| 431 | static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) |
| 432 | { |
| 433 | ulong start; |
| 434 | int flag; |
| 435 | FPWV *base; /* first address in flash bank */ |
| 436 | |
| 437 | /* Check if Flash is (sufficiently) erased */ |
| 438 | if ((*dest & data) != data) { |
| 439 | return (2); |
| 440 | } |
| 441 | |
| 442 | base = (FPWV *)(info->start[0]); |
| 443 | |
| 444 | /* Disable interrupts which might cause a timeout here */ |
| 445 | flag = disable_interrupts(); |
| 446 | |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 447 | base[FLASH_CYCLE1] = (FPW)0x00AA; /* unlock */ |
| 448 | base[FLASH_CYCLE2] = (FPW)0x0055; /* unlock */ |
| 449 | base[FLASH_CYCLE1] = (FPW)0x00A0; /* selects program mode */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 450 | |
| 451 | *dest = data; /* start programming the data */ |
| 452 | |
| 453 | /* re-enable interrupts if necessary */ |
| 454 | if (flag) |
| 455 | enable_interrupts(); |
| 456 | |
| 457 | start = get_timer (0); |
| 458 | |
| 459 | /* data polling for D7 */ |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 460 | while ((*dest & (FPW)0x0080) != (data & (FPW)0x0080)) { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 461 | if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
wdenk | b3a4a70 | 2004-12-10 11:40:40 +0000 | [diff] [blame] | 462 | *dest = (FPW)0x00F0; /* reset bank */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 463 | return (1); |
| 464 | } |
| 465 | } |
| 466 | return (0); |
| 467 | } |