blob: 7df16b047ceb01b595313dee316bc194eb94db51 [file] [log] [blame]
Michal Simeke116c542018-03-28 15:36:36 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
16
17/ {
18 model = "ZynqMP ZCU104 RevC";
19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem3;
23 gpio0 = &gpio;
24 i2c0 = &i2c1;
25 mmc0 = &sdhci1;
26 rtc0 = &rtc;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &dcc;
30 spi0 = &qspi;
31 usb0 = &usb0;
32 };
33
34 chosen {
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
Michal Simek53b97e62019-01-18 09:10:39 +010037 xlnx,eeprom = &eeprom;
Michal Simeke116c542018-03-28 15:36:36 +020038 };
39
40 memory@0 {
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
43 };
44};
45
46&can1 {
47 status = "okay";
48};
49
50&dcc {
51 status = "okay";
52};
53
54&gem3 {
55 status = "okay";
56 phy-handle = <&phy0>;
57 phy-mode = "rgmii-id";
58 phy0: phy@c {
59 reg = <0xc>;
60 ti,rx-internal-delay = <0x8>;
61 ti,tx-internal-delay = <0xa>;
62 ti,fifo-depth = <0x1>;
63 };
64};
65
66&gpio {
67 status = "okay";
68};
69
70&gpu {
71 status = "okay";
72};
73
74&i2c1 {
75 status = "okay";
76 clock-frequency = <400000>;
77
Michal Simekbea57132018-05-29 15:28:43 +020078 tca6416_u97: gpio@20 {
Michal Simeke116c542018-03-28 15:36:36 +020079 compatible = "ti,tca6416";
Michal Simekbea57132018-05-29 15:28:43 +020080 reg = <0x20>;
Michal Simeke116c542018-03-28 15:36:36 +020081 gpio-controller;
82 #gpio-cells = <2>;
83 /*
84 * IRQ not connected
85 * Lines:
86 * 0 - IRPS5401_ALERT_B
87 * 1 - HDMI_8T49N241_INT_ALM
88 * 2 - MAX6643_OT_B
89 * 3 - MAX6643_FANFAIL_B
90 * 5 - IIC_MUX_RESET_B
91 * 6 - GEM3_EXP_RESET_B
92 * 7 - FMC_LPC_PRSNT_M2C_B
93 * 4, 10 - 17 - not connected
94 */
95 };
96
97 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
98 i2c-mux@74 { /* u34 */
99 compatible = "nxp,pca9548";
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0x74>;
103 i2c@0 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <0>;
107 /*
108 * IIC_EEPROM 1kB memory which uses 256B blocks
109 * where every block has different address.
110 * 0 - 256B address 0x54
111 * 256B - 512B address 0x55
112 * 512B - 768B address 0x56
113 * 768B - 1024B address 0x57
114 */
115 eeprom: eeprom@54 { /* u23 */
116 compatible = "atmel,24c08";
117 reg = <0x54>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 };
121 };
122
123 i2c@1 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 reg = <1>;
127 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
128 compatible = "idt,8t49n287";
129 reg = <0x6c>;
130 };
131 };
132
133 i2c@2 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 reg = <2>;
137 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
138 #clock-cells = <0>;
139 compatible = "infineon,irps5401";
140 reg = <0x43>;
141 };
142 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
143 #clock-cells = <0>;
144 compatible = "infineon,irps5401";
145 reg = <0x4d>;
146 };
147 };
148
Michal Simekee29db12018-05-29 14:45:13 +0200149 i2c@3 {
Michal Simeke116c542018-03-28 15:36:36 +0200150 #address-cells = <1>;
151 #size-cells = <0>;
Michal Simekee29db12018-05-29 14:45:13 +0200152 reg = <3>;
153 ina226@40 { /* u183 */
154 compatible = "ti,ina226";
155 reg = <0x40>;
156 shunt-resistor = <5000>;
157 };
Michal Simeke116c542018-03-28 15:36:36 +0200158 };
159
160 i2c@5 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 reg = <5>;
164 };
165
166 i2c@7 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 reg = <7>;
170 };
171
Michal Simekee29db12018-05-29 14:45:13 +0200172 /* 4, 6 not connected */
Michal Simeke116c542018-03-28 15:36:36 +0200173 };
174};
175
176&qspi {
177 status = "okay";
178 flash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000179 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
Michal Simeke116c542018-03-28 15:36:36 +0200180 #address-cells = <1>;
181 #size-cells = <1>;
182 reg = <0x0>;
183 spi-tx-bus-width = <1>;
184 spi-rx-bus-width = <4>;
185 spi-max-frequency = <108000000>; /* Based on DC1 spec */
186 partition@qspi-fsbl-uboot { /* for testing purpose */
187 label = "qspi-fsbl-uboot";
188 reg = <0x0 0x100000>;
189 };
190 partition@qspi-linux { /* for testing purpose */
191 label = "qspi-linux";
192 reg = <0x100000 0x500000>;
193 };
194 partition@qspi-device-tree { /* for testing purpose */
195 label = "qspi-device-tree";
196 reg = <0x600000 0x20000>;
197 };
198 partition@qspi-rootfs { /* for testing purpose */
199 label = "qspi-rootfs";
200 reg = <0x620000 0x5E0000>;
201 };
202 };
203};
204
205&rtc {
206 status = "okay";
207};
208
209&sata {
210 status = "okay";
211 /* SATA OOB timing settings */
212 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
213 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
214 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
215 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
216 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
217 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
218 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
219 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
220 phy-names = "sata-phy";
221 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
222};
223
224/* SD1 with level shifter */
225&sdhci1 {
226 status = "okay";
227 no-1-8-v;
228 xlnx,mio_bank = <1>;
229 disable-wp;
230};
231
232&serdes {
233 status = "okay";
234};
235
236&uart0 {
237 status = "okay";
238};
239
240&uart1 {
241 status = "okay";
242};
243
244/* ULPI SMSC USB3320 */
245&usb0 {
246 status = "okay";
247};
248
249&dwc3_0 {
250 status = "okay";
251 dr_mode = "host";
252 snps,usb3_lpm_capable;
253 phy-names = "usb3-phy";
254 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
255 maximum-speed = "super-speed";
256};
257
258&watchdog0 {
259 status = "okay";
260};
261
262&xilinx_ams {
263 status = "okay";
264};
265
266&ams_ps {
267 status = "okay";
268};
269
270&ams_pl {
271 status = "okay";
272};