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Patrice Chotard00442d02019-02-12 16:50:38 +01001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp157-u-boot.dtsi"
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11 aliases {
12 i2c3 = &i2c4;
13 mmc0 = &sdmmc1;
Patrick Delaunay58bc0cd2019-03-29 15:42:23 +010014 usb0 = &usbotg_hs;
Patrice Chotard00442d02019-02-12 16:50:38 +010015 };
16 config {
17 u-boot,boot-led = "heartbeat";
18 u-boot,error-led = "error";
19 st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
20 };
21 led {
22 red {
23 label = "error";
24 gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
25 default-state = "off";
26 status = "okay";
27 };
28
29 blue {
30 default-state = "on";
31 };
32 };
33};
34
Patrice Chotarde861c202019-02-12 16:50:41 +010035&adc {
36 pinctrl-names = "default";
37 pinctrl-0 = <&adc12_usb_pwr_pins_a>;
38 vdd-supply = <&vdd>;
39 vdda-supply = <&vdd>;
40 vref-supply = <&vrefbuf>;
41 status = "okay";
42 adc1: adc@0 {
43 /*
44 * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
45 * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
46 * 5 * (56 + 47kOhms) * 5pF => 2.5us.
47 * Use arbitrary margin here (e.g. 5µs).
48 */
49 st,min-sample-time-nsecs = <5000>;
50 /* ANA0, ANA1, USB Type-C CC1 & CC2 */
51 st,adc-channels = <0 1 18 19>;
52 status = "okay";
53 };
54};
55
Patrice Chotard00442d02019-02-12 16:50:38 +010056&clk_hse {
57 st,digbypass;
58};
59
60&i2c4 {
61 u-boot,dm-pre-reloc;
62};
63
64&i2c4_pins_a {
65 u-boot,dm-pre-reloc;
66 pins {
67 u-boot,dm-pre-reloc;
68 };
69};
70
71&pmic {
72 u-boot,dm-pre-reloc;
73};
74
75&rcc {
76 st,clksrc = <
77 CLK_MPU_PLL1P
78 CLK_AXI_PLL2P
79 CLK_MCU_PLL3P
80 CLK_PLL12_HSE
81 CLK_PLL3_HSE
82 CLK_PLL4_HSE
83 CLK_RTC_LSE
84 CLK_MCO1_DISABLED
85 CLK_MCO2_DISABLED
86 >;
87
88 st,clkdiv = <
89 1 /*MPU*/
90 0 /*AXI*/
91 0 /*MCU*/
92 1 /*APB1*/
93 1 /*APB2*/
94 1 /*APB3*/
95 1 /*APB4*/
96 2 /*APB5*/
97 23 /*RTC*/
98 0 /*MCO1*/
99 0 /*MCO2*/
100 >;
101
102 st,pkcs = <
103 CLK_CKPER_HSE
104 CLK_FMC_ACLK
105 CLK_QSPI_ACLK
106 CLK_ETH_DISABLED
107 CLK_SDMMC12_PLL4P
108 CLK_DSI_DSIPLL
109 CLK_STGEN_HSE
110 CLK_USBPHY_HSE
111 CLK_SPI2S1_PLL3Q
112 CLK_SPI2S23_PLL3Q
113 CLK_SPI45_HSI
114 CLK_SPI6_HSI
115 CLK_I2C46_HSI
116 CLK_SDMMC3_PLL4P
117 CLK_USBO_USBPHY
118 CLK_ADC_CKPER
119 CLK_CEC_LSE
120 CLK_I2C12_HSI
121 CLK_I2C35_HSI
122 CLK_UART1_HSI
123 CLK_UART24_HSI
124 CLK_UART35_HSI
125 CLK_UART6_HSI
126 CLK_UART78_HSI
127 CLK_SPDIF_PLL4P
128 CLK_FDCAN_PLL4Q
129 CLK_SAI1_PLL3Q
130 CLK_SAI2_PLL3Q
131 CLK_SAI3_PLL3Q
132 CLK_SAI4_PLL3Q
133 CLK_RNG1_LSI
134 CLK_RNG2_LSI
135 CLK_LPTIM1_PCLK1
136 CLK_LPTIM23_PCLK3
137 CLK_LPTIM45_LSE
138 >;
139
140 /* VCO = 1300.0 MHz => P = 650 (CPU) */
141 pll1: st,pll@0 {
142 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
143 frac = < 0x800 >;
144 u-boot,dm-pre-reloc;
145 };
146
147 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
148 pll2: st,pll@1 {
149 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
150 frac = < 0x1400 >;
151 u-boot,dm-pre-reloc;
152 };
153
154 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
155 pll3: st,pll@2 {
156 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
157 frac = < 0x1a04 >;
158 u-boot,dm-pre-reloc;
159 };
160
161 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
162 pll4: st,pll@3 {
163 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
164 u-boot,dm-pre-reloc;
165 };
166};
167
168&sdmmc1 {
169 u-boot,dm-spl;
170};
171
172&sdmmc1_b4_pins_a {
173 u-boot,dm-spl;
174 pins {
175 u-boot,dm-spl;
176 };
177};
178
179&uart4 {
180 u-boot,dm-pre-reloc;
181};
182
183&uart4_pins_a {
184 u-boot,dm-pre-reloc;
185 pins1 {
186 u-boot,dm-pre-reloc;
187 };
188 pins2 {
189 u-boot,dm-pre-reloc;
190 };
191};
192
193&usbotg_hs {
Patrick Delaunay7f3384d2019-03-29 15:42:24 +0100194 u-boot,force-b-session-valid;
Patrice Chotard00442d02019-02-12 16:50:38 +0100195 hnp-srp-disable;
196};