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git01.mediatek.com / filogic / uboot / 400b06f41eb28b34e3142b64ad949ed0bf693fc6 / . / arch / arm / dts / imx7-colibri.dtsi
blob: b352036e304f9df627de5d228e5d3b5d14de1eea [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]2/*
Stefan Agnerdfe41da2019-01-08 12:42:29 +0100[diff] [blame]3 * Copyright 2016-2019 Toradex AG
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]4 */
5
6/dts-v1/;
7#include <dt-bindings/gpio/gpio.h>
Peng Faneab61a22017-04-13 14:09:49 +0800[diff] [blame]8#include "imx7d.dtsi"
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]9
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]10&i2c1 {
11 pinctrl-names = "default", "gpio";
12 pinctrl-0 = <&pinctrl_i2c1>;
13 pinctrl-1 = <&pinctrl_i2c1_gpio>;
14 sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
15 scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
16 status = "okay";
Stefan Agnerfd8bb692016-10-05 15:27:10 -0700[diff] [blame]17
18 rn5t567@33 {
19 compatible = "ricoh,rn5t567";
20 reg = <0x33>;
Igor Opaniuk329a6482019-11-04 11:12:03 +0100[diff] [blame]21
22 regulators {
23 reg_DCDC1: DCDC1 { /* V1.0_SOC */
24 regulator-min-microvolt = <1000000>;
25 regulator-max-microvolt = <1100000>;
26 regulator-boot-on;
27 regulator-always-on;
28 };
29
30 reg_DCDC2: DCDC2 { /* V1.1_ARM */
31 regulator-min-microvolt = <975000>;
32 regulator-max-microvolt = <1100000>;
33 regulator-boot-on;
34 regulator-always-on;
35 };
36
37 reg_DCDC3: DCDC3 { /* V1.8 */
38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvolt = <1800000>;
40 regulator-boot-on;
41 regulator-always-on;
42 };
43
44 reg_DCDC4: DCDC4 { /* V1.35_DRAM */
45 regulator-min-microvolt = <1350000>;
46 regulator-max-microvolt = <1350000>;
47 regulator-boot-on;
48 regulator-always-on;
49 };
50
51 reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <3300000>;
54 regulator-boot-on;
55 };
56
57 reg_LDO2: LDO2 { /* +V1.8_SD */
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <3300000>;
60 regulator-boot-on;
61 regulator-always-on;
62 };
63
64 reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>;
67 regulator-boot-on;
68 regulator-always-on;
69 };
70
71 reg_LDO4: LDO4 { /* V1.8_LPSR */
72 regulator-min-microvolt = <1800000>;
73 regulator-max-microvolt = <1800000>;
74 regulator-boot-on;
75 regulator-always-on;
76 };
77
78 reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
81 regulator-boot-on;
82 regulator-always-on;
83 };
84 };
Stefan Agnerfd8bb692016-10-05 15:27:10 -0700[diff] [blame]85 };
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]86};
87
88&i2c4 {
89 pinctrl-names = "default", "gpio";
90 pinctrl-0 = <&pinctrl_i2c4>;
91 pinctrl-1 = <&pinctrl_i2c4_gpio>;
92 sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
93 scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
94 status = "okay";
95};
96
Igor Opaniuk329a6482019-11-04 11:12:03 +0100[diff] [blame]97&fec1 {
98 pinctrl-names = "default", "sleep";
99 pinctrl-0 = <&pinctrl_enet1>;
100 pinctrl-1 = <&pinctrl_enet1_sleep>;
101 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
102 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
103 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
104 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
105 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
106 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
107 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
108 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
109 assigned-clock-rates = <0>, <100000000>;
110 phy-mode = "rmii";
111 phy-supply = <&reg_LDO1>;
112 fsl,magic-packet;
113 status = "okay";
114};
115
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]116&uart1 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
119 uart-has-rtscts;
120 fsl,dte-mode;
121 status = "okay";
122};
123
Stefan Agnerc9fc1f12019-01-08 12:42:32 +0100[diff] [blame]124&usdhc1 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
127 no-1-8-v;
128 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
129 disable-wp;
130 status = "okay";
131};
132
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]133&iomuxc {
134 pinctrl_i2c4: i2c4-grp {
135 fsl,pins = <
136 MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
137 MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
138 >;
139 };
140
141 pinctrl_i2c4_gpio: i2c4-gpio-grp {
142 fsl,pins = <
143 MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
144 MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
145 >;
146 };
147
148 pinctrl_uart1: uart1-grp {
149 fsl,pins = <
150 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
151 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
152 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
153 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
154 >;
155 };
156
157 pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
158 fsl,pins = <
159 MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
160 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
161 >;
162 };
Stefan Agnerc9fc1f12019-01-08 12:42:32 +0100[diff] [blame]163
164 pinctrl_usdhc1: usdhc1-grp {
165 fsl,pins = <
166 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
167 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
168 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
169 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
170 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
171 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
172 >;
173 };
Igor Opaniuk329a6482019-11-04 11:12:03 +0100[diff] [blame]174
Igor Opaniuk2213c892020-07-15 13:31:02 +0300[diff] [blame]175 pinctrl_lcdif_dat: lcdif-dat-grp {
176 fsl,pins = <
177 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
178 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
179 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
180 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
181 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
182 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
183 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
184 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
185 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
186 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
187 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
188 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
189 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
190 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
191 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
192 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
193 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
194 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
195 >;
196 };
197
198 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
199 fsl,pins = <
200 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
201 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
202 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
203 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
204 >;
205 };
206
Igor Opaniuk329a6482019-11-04 11:12:03 +0100[diff] [blame]207 pinctrl_enet1: enet1grp {
208 fsl,pins = <
209 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
210 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
211 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
212 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
213 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
214
215 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
216 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
217 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
218 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
219 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
220 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
221 >;
222 };
223
224 pinctrl_enet1_sleep: enet1sleepgrp {
225 fsl,pins = <
226 MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
227 MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
228 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
229 MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
230
231 MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
232 MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
233 MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
234 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
235 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
236 MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
237 >;
238 };
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]239};
240
241&iomuxc_lpsr {
242 pinctrl_i2c1: i2c1-grp {
243 fsl,pins = <
Peng Faneab61a22017-04-13 14:09:49 +0800[diff] [blame]244 MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
245 MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]246 >;
247 };
248
249 pinctrl_i2c1_gpio: i2c1-gpio-grp {
250 fsl,pins = <
Peng Faneab61a22017-04-13 14:09:49 +0800[diff] [blame]251 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
252 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]253 >;
254 };
Stefan Agnerc9fc1f12019-01-08 12:42:32 +0100[diff] [blame]255
256 pinctrl_cd_usdhc1: usdhc1-cd-grp {
257 fsl,pins = <
258 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
259 >;
260 };
Stefan Agner1ad129a2016-10-05 15:27:06 -0700[diff] [blame]261};