Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 400667d7325c1fa24c9dbcc13470a3ee8f43b650 / . / board / keymile / mgcoge / mgcoge.c
blob: 6dda92062b5559c697d87090d4bec942391c8b6b [file] [log] [blame]
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]1/*
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]2 * (C) Copyright 2007 - 2008
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc8260.h>
26#include <ioports.h>
Heiko Schocher65138e12008-10-15 09:36:03 +0200[diff] [blame]27#include <malloc.h>
Heiko Schocher012a95f2008-10-17 12:15:55 +0200[diff] [blame]28#include <asm/io.h>
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]29
30#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
31#include <libfdt.h>
32#endif
33
Heiko Schocher65138e12008-10-15 09:36:03 +0200[diff] [blame]34#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
35#include <i2c.h>
36#endif
37
Heiko Schochere5b6c2e2008-10-15 09:41:00 +0200[diff] [blame]38extern int ivm_read_eeprom (void);
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]39/*
40 * I/O Port configuration table
41 *
42 * if conf is 1, then that port pin will be configured at boot time
43 * according to the five values podr/pdir/ppar/psor/pdat for that entry
44 */
45const iop_conf_t iop_conf_tab[4][32] = {
46
47 /* Port A */
48 { /* conf ppar psor pdir podr pdat */
49 /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
50 /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
51 /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
52 /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
53 /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
54 /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
55 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
56 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
57 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
58 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
59 /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
60 /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
61 /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
62 /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
63 /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
64 /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
65 /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
66 /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
67 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
68 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
69 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
70 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
71 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
72 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
73 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
74 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
75 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
76 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
77 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
78 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
79 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
80 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
81 },
82
83 /* Port B */
84 { /* conf ppar psor pdir podr pdat */
85 /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
86 /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
87 /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
88 /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
89 /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
90 /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
91 /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
92 /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
93 /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
94 /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
95 /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
96 /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
97 /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
98 /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
99 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
100 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
101 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
102 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
103 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
104 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
105 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
106 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
107 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
108 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
109 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
110 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
111 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
112 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
113 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
114 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
115 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
116 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
117 },
118
119 /* Port C */
120 { /* conf ppar psor pdir podr pdat */
121 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
122 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
123 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
124 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
125 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
126 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
127 /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
128 /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
129 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
130 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
131 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
132 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
133 /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
134 /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
135 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
136 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
137 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
138 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
139 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
140 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
141 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
142 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
143 /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
144 /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
145 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
146 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
147 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
148 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
149 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
150 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
151 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
152 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
153 },
154
155 /* Port D */
156 { /* conf ppar psor pdir podr pdat */
157 /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
158 /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
159 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
160 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
161 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
162 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
163 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
164 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
165 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
166 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
167 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
168 /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
169 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
170 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
171 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
172 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
Heiko Schocher65138e12008-10-15 09:36:03 +0200[diff] [blame]173#if defined(CONFIG_HARD_I2C)
174 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
175 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
176#else
177 /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
178 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
179#endif
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]180 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
181 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
182 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
183 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
184 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
185 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
186 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
187 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
188 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
189 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
190 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
191 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
192 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
193 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
194 }
195};
196
197/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
198 *
199 * This routine performs standard 8260 initialization sequence
200 * and calculates the available memory size. It may be called
201 * several times to try different SDRAM configurations on both
202 * 60x and local buses.
203 */
204static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
205 ulong orx, volatile uchar * base)
206{
207 volatile uchar c = 0xff;
208 volatile uint *sdmr_ptr;
209 volatile uint *orx_ptr;
210 ulong maxsize, size;
211 int i;
212
213 /* We must be able to test a location outsize the maximum legal size
214 * to find out THAT we are outside; but this address still has to be
215 * mapped by the controller. That means, that the initial mapping has
216 * to be (at least) twice as large as the maximum expected size.
217 */
218 maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
219
220 sdmr_ptr = &memctl->memc_psdmr;
221 orx_ptr = &memctl->memc_or1;
222
223 *orx_ptr = orx;
224
225 /*
226 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
227 *
228 * "At system reset, initialization software must set up the
229 * programmable parameters in the memory controller banks registers
230 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
231 * system software should execute the following initialization sequence
232 * for each SDRAM device.
233 *
234 * 1. Issue a PRECHARGE-ALL-BANKS command
235 * 2. Issue eight CBR REFRESH commands
236 * 3. Issue a MODE-SET command to initialize the mode register
237 *
238 * The initial commands are executed by setting P/LSDMR[OP] and
239 * accessing the SDRAM with a single-byte transaction."
240 *
241 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]242 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]243 */
244
245 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
246 *base = c;
247
248 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
249 for (i = 0; i < 8; i++)
250 *base = c;
251
252 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]253 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]254
255 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
256 *base = c;
257
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]258 size = get_ram_size ((long *)base, maxsize);
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]259 *orx_ptr = orx | ~(size - 1);
260
261 return (size);
262}
263
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]264phys_size_t initdram (int board_type)
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]265{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]266 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]267 volatile memctl8260_t *memctl = &immap->im_memctl;
268
269 long psize;
270
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]271 memctl->memc_psrt = CONFIG_SYS_PSRT;
272 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]273
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]274#ifndef CONFIG_SYS_RAMBOOT
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]275 /* 60x SDRAM setup:
276 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]277 psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
278 (uchar *) CONFIG_SYS_SDRAM_BASE);
279#endif /* CONFIG_SYS_RAMBOOT */
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]280
281 icache_enable ();
282
283 return (psize);
284}
285
286int checkboard(void)
287{
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]288 puts ("Board: mgcoge\n");
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]289
290 return 0;
291}
292
Heiko Schochera83cbee2008-03-07 08:13:41 +0100[diff] [blame]293/*
294 * Early board initalization.
295 */
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]296int board_early_init_r (void)
Heiko Schochera83cbee2008-03-07 08:13:41 +0100[diff] [blame]297{
298 /* setup the UPIOx */
Heiko Schocher012a95f2008-10-17 12:15:55 +0200[diff] [blame]299 out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0);
300 out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15);
Heiko Schochera83cbee2008-03-07 08:13:41 +0100[diff] [blame]301 return 0;
302}
303
Heiko Schochere5b6c2e2008-10-15 09:41:00 +0200[diff] [blame]304int hush_init_var (void)
305{
306 ivm_read_eeprom ();
307 return 0;
308}
309
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]310#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
Heiko Schocher1eedd3f2008-10-17 16:11:52 +0200[diff] [blame]311extern int fdt_set_node_and_value (void *blob,
312 char *nodename,
313 char *regname,
314 void *var,
315 int size);
316
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]317/*
318 * update "memory" property in the blob
319 */
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]320void ft_blob_update (void *blob, bd_t *bd)
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]321{
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]322 ulong memory_data[2] = {0};
Heiko Schochera83cbee2008-03-07 08:13:41 +0100[diff] [blame]323 ulong flash_data[8] = {0};
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]324
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]325 memory_data[0] = cpu_to_be32 (bd->bi_memstart);
326 memory_data[1] = cpu_to_be32 (bd->bi_memsize);
Heiko Schocher1eedd3f2008-10-17 16:11:52 +0200[diff] [blame]327 fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
328 sizeof (memory_data));
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]329
Heiko Schochera83cbee2008-03-07 08:13:41 +0100[diff] [blame]330 /* update Flash addr, size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]331 flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
332 flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
Heiko Schocher63d03de2008-10-17 12:13:30 +0200[diff] [blame]333 flash_data[4] = cpu_to_be32 (5);
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]334 flash_data[5] = cpu_to_be32 (0);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]335 flash_data[6] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1);
336 flash_data[7] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE_1);
Heiko Schocher1eedd3f2008-10-17 16:11:52 +0200[diff] [blame]337 fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
338 sizeof (flash_data));
339 /* MAC addr */
340 fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
341 bd->bi_enetaddr, sizeof (u8) * 6);
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]342}
343
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]344void ft_board_setup (void *blob, bd_t *bd)
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]345{
Heiko Schocher43921062008-10-15 09:34:05 +0200[diff] [blame]346 ft_cpu_setup (blob, bd);
347 ft_blob_update (blob, bd);
Heiko Schocher30de2ed2008-01-11 01:12:08 +0100[diff] [blame]348}
349#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */