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git01.mediatek.com / filogic / uboot / 400667d7325c1fa24c9dbcc13470a3ee8f43b650 / . / board / esd / dp405 / u-boot.lds
blob: 7ff074c152ed5a6369351280009248d6a52b76e6 [file] [log] [blame]
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_ARCH(powerpc)
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]25/* Do we need any of these for elf?
26 __DYNAMIC = 0; */
27SECTIONS
28{
29 .resetvec 0xFFFFFFFC :
30 {
31 *(.resetvec)
32 } = 0xffff
33
34 /* Read-only sections, merged into text segment: */
35 . = + SIZEOF_HEADERS;
36 .interp : { *(.interp) }
37 .hash : { *(.hash) }
38 .dynsym : { *(.dynsym) }
39 .dynstr : { *(.dynstr) }
40 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]41 .rela.text : { *(.rela.text) }
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]42 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]43 .rela.data : { *(.rela.data) }
44 .rel.rodata : { *(.rel.rodata) }
45 .rela.rodata : { *(.rela.rodata) }
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]46 .rel.got : { *(.rel.got) }
47 .rela.got : { *(.rela.got) }
48 .rel.ctors : { *(.rel.ctors) }
49 .rela.ctors : { *(.rela.ctors) }
50 .rel.dtors : { *(.rel.dtors) }
51 .rela.dtors : { *(.rela.dtors) }
52 .rel.bss : { *(.rel.bss) }
53 .rela.bss : { *(.rela.bss) }
54 .rel.plt : { *(.rel.plt) }
55 .rela.plt : { *(.rela.plt) }
56 .init : { *(.init) }
57 .plt : { *(.plt) }
58 .text :
59 {
60 /* WARNING - the following is hand-optimized to fit within */
61 /* the sector layout of our flash chips! XXX FIXME XXX */
62
63 cpu/ppc4xx/start.o (.text)
64 cpu/ppc4xx/traps.o (.text)
65 cpu/ppc4xx/interrupts.o (.text)
Stefan Roesef82271e2007-10-22 15:44:39 +0200[diff] [blame]66 cpu/ppc4xx/4xx_uart.o (.text)
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]67 cpu/ppc4xx/cpu_init.o (.text)
68 cpu/ppc4xx/speed.o (.text)
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200[diff] [blame]69 cpu/ppc4xx/4xx_enet.o (.text)
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]70 common/dlmalloc.o (.text)
71 lib_generic/crc32.o (.text)
72 lib_ppc/extable.o (.text)
73 lib_generic/zlib.o (.text)
74
75/* . = env_offset;*/
Jean-Christophe PLAGNIOL-VILLARD4436c1e2008-09-10 22:48:01 +0200[diff] [blame]76/* common/env_embedded.o(.text)*/
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]77
78 *(.text)
79 *(.fixup)
80 *(.got1)
81 }
82 _etext = .;
83 PROVIDE (etext = .);
84 .rodata :
85 {
86 *(.rodata)
87 *(.rodata1)
88 *(.rodata.str1.4)
Wolfgang Denkaaa7c002005-12-12 16:06:05 +0100[diff] [blame]89 *(.eh_frame)
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]90 }
91 .fini : { *(.fini) } =0
92 .ctors : { *(.ctors) }
93 .dtors : { *(.dtors) }
94
95 /* Read-write section, merged into data segment: */
96 . = (. + 0x00FF) & 0xFFFFFF00;
97 _erotext = .;
98 PROVIDE (erotext = .);
99 .reloc :
100 {
101 *(.got)
102 _GOT2_TABLE_ = .;
103 *(.got2)
104 _FIXUP_TABLE_ = .;
105 *(.fixup)
106 }
107 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
108 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
109
110 .data :
111 {
112 *(.data)
113 *(.data1)
114 *(.sdata)
115 *(.sdata2)
116 *(.dynamic)
117 CONSTRUCTORS
118 }
119 _edata = .;
120 PROVIDE (edata = .);
121
Wolfgang Denk5dd2c652005-08-31 12:28:00 +0200[diff] [blame]122 . = .;
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]123 __u_boot_cmd_start = .;
124 .u_boot_cmd : { *(.u_boot_cmd) }
125 __u_boot_cmd_end = .;
126
127
Wolfgang Denk5dd2c652005-08-31 12:28:00 +0200[diff] [blame]128 . = .;
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]129 __start___ex_table = .;
130 __ex_table : { *(__ex_table) }
131 __stop___ex_table = .;
132
133 . = ALIGN(256);
134 __init_begin = .;
135 .text.init : { *(.text.init) }
136 .data.init : { *(.data.init) }
137 . = ALIGN(256);
138 __init_end = .;
139
140 __bss_start = .;
Wolfgang Denk828a9782008-01-12 20:31:39 +0100[diff] [blame]141 .bss (NOLOAD) :
stroesede46bb62003-09-12 08:41:24 +0000[diff] [blame]142 {
143 *(.sbss) *(.scommon)
144 *(.dynbss)
145 *(.bss)
146 *(COMMON)
147 }
148 _end = . ;
149 PROVIDE (end = .);
150}