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git01.mediatek.com / filogic / uboot / 400667d7325c1fa24c9dbcc13470a3ee8f43b650 / . / board / dave / B2 / lowlevel_init.S
blob: 2f3a3645ed60e28563992d3ea20184b14516b33f [file] [log] [blame]
wdenkb98ac282004-02-24 00:16:43 +0000[diff] [blame]1/*
2 * (C) Copyright 2004
3 * DAVE Srl
4 *
5 * http://www.dave-tech.it
6 * http://www.wawnet.biz
7 * mailto:info@wawnet.biz
8 *
9 * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
10 * Modified By MATTO
11 *
12 * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30/*
31 * Documentation:
32 * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
33 * Advanced Developer's manual, December 1999
34 *
35 * Intel has a very hard to find SDRAM configurator on their web site:
36 * http://appzone.intel.com/hcd/sa1110/memory/index.asp
37 *
38 * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
39 * appears to be true, but it might be possible that somebody designs a
40 * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
41 *
42 * 04-10-2001: SELETZ
43 * - separated memory config for multiple platform support
44 * - perform SA1110 Hardware Reset Procedure
45 *
46 */
47
48.equ B0_Tacs, 0x0 /* 0clk */
49.equ B0_Tcos, 0x0 /* 0clk */
50.equ B0_Tacc, 0x4 /* 6clk */
51.equ B0_Tcoh, 0x0 /* 0clk */
52.equ B0_Tah, 0x0 /* 0clk */
53.equ B0_Tacp, 0x0 /* 0clk */
54.equ B0_PMC, 0x0 /* normal(1data) */
55/* Bank 1 parameter */
56.equ B1_Tacs, 0x3 /* 4clk */
57.equ B1_Tcos, 0x3 /* 4clk */
58.equ B1_Tacc, 0x7 /* 14clkv */
59.equ B1_Tcoh, 0x3 /* 4clk */
60.equ B1_Tah, 0x3 /* 4clk */
61.equ B1_Tacp, 0x3 /* 6clk */
62.equ B1_PMC, 0x0 /* normal(1data) */
63
64/* Bank 2 parameter - LAN91C96 */
65.equ B2_Tacs, 0x3 /* 4clk */
66.equ B2_Tcos, 0x3 /* 4clk */
67.equ B2_Tacc, 0x7 /* 14clk */
68.equ B2_Tcoh, 0x3 /* 4clk */
69.equ B2_Tah, 0x3 /* 4clk */
70.equ B2_Tacp, 0x3 /* 6clk */
71.equ B2_PMC, 0x0 /* normal(1data) */
72
73/* Bank 3 parameter */
74.equ B3_Tacs, 0x3 /* 4clk */
75.equ B3_Tcos, 0x3 /* 4clk */
76.equ B3_Tacc, 0x7 /* 14clk */
77.equ B3_Tcoh, 0x3 /* 4clk */
78.equ B3_Tah, 0x3 /* 4clk */
79.equ B3_Tacp, 0x3 /* 6clk */
80.equ B3_PMC, 0x0 /* normal(1data) */
81
82/* Bank 4 parameter */
83.equ B4_Tacs, 0x3 /* 4clk */
84.equ B4_Tcos, 0x3 /* 4clk */
85.equ B4_Tacc, 0x7 /* 14clk */
86.equ B4_Tcoh, 0x3 /* 4clk */
87.equ B4_Tah, 0x3 /* 4clk */
88.equ B4_Tacp, 0x3 /* 6clk */
89.equ B4_PMC, 0x0 /* normal(1data) */
90
91/* Bank 5 parameter */
92.equ B5_Tacs, 0x3 /* 4clk */
93.equ B5_Tcos, 0x3 /* 4clk */
94.equ B5_Tacc, 0x7 /* 14clk */
95.equ B5_Tcoh, 0x3 /* 4clk */
96.equ B5_Tah, 0x3 /* 4clk */
97.equ B5_Tacp, 0x3 /* 6clk */
98.equ B5_PMC, 0x0 /* normal(1data) */
99
100/* Bank 6(if SROM) parameter */
101.equ B6_Tacs, 0x3 /* 4clk */
102.equ B6_Tcos, 0x3 /* 4clk */
103.equ B6_Tacc, 0x7 /* 14clk */
104.equ B6_Tcoh, 0x3 /* 4clk */
105.equ B6_Tah, 0x3 /* 4clk */
106.equ B6_Tacp, 0x3 /* 6clk */
107.equ B6_PMC, 0x0 /* normal(1data) */
108
109/* Bank 7(if SROM) parameter */
110.equ B7_Tacs, 0x3 /* 4clk */
111.equ B7_Tcos, 0x3 /* 4clk */
112.equ B7_Tacc, 0x7 /* 14clk */
113.equ B7_Tcoh, 0x3 /* 4clk */
114.equ B7_Tah, 0x3 /* 4clk */
115.equ B7_Tacp, 0x3 /* 6clk */
116.equ B7_PMC, 0x0 /* normal(1data) */
117
118/* Bank 6 parameter */
119.equ B6_MT, 0x3 /* SDRAM */
120.equ B6_Trcd, 0x0 /* 2clk */
121.equ B6_SCAN, 0x0 /* 10bit */
122
123.equ B7_MT, 0x3 /* SDRAM */
124.equ B7_Trcd, 0x0 /* 2clk */
125.equ B7_SCAN, 0x0 /* 10bit */
126
127
128/* REFRESH parameter */
129.equ REFEN, 0x1 /* Refresh enable */
130.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */
131.equ Trp, 0x0 /* 2clk */
132.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/
133.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */
134.equ REFCNT, 879
135
136MEMORY_CONFIG:
137 .long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
138 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
139 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
140 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
141 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
142 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
143 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
144 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/
145 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/
146 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
147 .word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/
148 .word 0x20 /*MRSR6 CL=2clk*/
149 .word 0x20 /*MRSR7*/
150
151
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]152.globl lowlevel_init
153lowlevel_init:
wdenkb98ac282004-02-24 00:16:43 +0000[diff] [blame]154
155 /*
156 the next instruction fail due memory relocation...
157 we'll find the right MEMORY_CONFIG address with the next 3 lines...
158 */
159 /*ldr r0, =MEMORY_CONFIG*/
160 mov r0, pc
161 ldr r1, =(0x38+4)
162 sub r0, r0, r1
163
164 ldmia r0, {r1-r13}
165 ldr r0, =0x01c80000
166 stmia r0, {r1-r13}
167 mov pc, lr