blob: e831d3797d18e1aaa671d0a6c0952c6a2e447e26 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sun03017032015-03-20 19:28:23 -07002/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2017, 2019-2021 NXP
York Sun03017032015-03-20 19:28:23 -07004 * Copyright 2015 Freescale Semiconductor
York Sun03017032015-03-20 19:28:23 -07005 */
6
7#ifndef __LS2_QDS_H
8#define __LS2_QDS_H
9
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053010#include "ls2080a_common.h"
York Sun03017032015-03-20 19:28:23 -070011
York Sun03017032015-03-20 19:28:23 -070012#ifndef __ASSEMBLY__
13unsigned long get_board_sys_clk(void);
York Sun03017032015-03-20 19:28:23 -070014#endif
15
Yuan Yao5a89cce2016-06-08 18:24:54 +080016#ifdef CONFIG_FSL_QSPI
Yuan Yao5a89cce2016-06-08 18:24:54 +080017#define CONFIG_QIXIS_I2C_ACCESS
Yuan Yao5a89cce2016-06-08 18:24:54 +080018#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
19#endif
20
21#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
York Sun03017032015-03-20 19:28:23 -070022#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
York Sun03017032015-03-20 19:28:23 -070023#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
24
York Sun03017032015-03-20 19:28:23 -070025#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
26#define SPD_EEPROM_ADDRESS1 0x51
27#define SPD_EEPROM_ADDRESS2 0x52
28#define SPD_EEPROM_ADDRESS3 0x53
29#define SPD_EEPROM_ADDRESS4 0x54
30#define SPD_EEPROM_ADDRESS5 0x55
31#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
32#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
33#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
34#define CONFIG_DIMM_SLOTS_PER_CTLR 2
35#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053036#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sun03017032015-03-20 19:28:23 -070037#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053038#endif
York Sun03017032015-03-20 19:28:23 -070039
Tang Yuantian57894be2015-12-09 15:32:18 +080040/* SATA */
Tang Yuantian57894be2015-12-09 15:32:18 +080041#define CONFIG_SCSI_AHCI_PLAT
Tang Yuantian57894be2015-12-09 15:32:18 +080042
43#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
44#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
45
46#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
47#define CONFIG_SYS_SCSI_MAX_LUN 1
48#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
49 CONFIG_SYS_SCSI_MAX_LUN)
50
York Sun03017032015-03-20 19:28:23 -070051#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
52#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
53#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
54
55#define CONFIG_SYS_NOR0_CSPR \
56 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
57 CSPR_PORT_SIZE_16 | \
58 CSPR_MSEL_NOR | \
59 CSPR_V)
60#define CONFIG_SYS_NOR0_CSPR_EARLY \
61 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
62 CSPR_PORT_SIZE_16 | \
63 CSPR_MSEL_NOR | \
64 CSPR_V)
65#define CONFIG_SYS_NOR1_CSPR \
66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
67 CSPR_PORT_SIZE_16 | \
68 CSPR_MSEL_NOR | \
69 CSPR_V)
70#define CONFIG_SYS_NOR1_CSPR_EARLY \
71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
72 CSPR_PORT_SIZE_16 | \
73 CSPR_MSEL_NOR | \
74 CSPR_V)
75#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
76#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
77 FTIM0_NOR_TEADC(0x5) | \
78 FTIM0_NOR_TEAHC(0x5))
79#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
80 FTIM1_NOR_TRAD_NOR(0x1a) |\
81 FTIM1_NOR_TSEQRAD_NOR(0x13))
82#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
83 FTIM2_NOR_TCH(0x4) | \
84 FTIM2_NOR_TWPH(0x0E) | \
85 FTIM2_NOR_TWP(0x1c))
86#define CONFIG_SYS_NOR_FTIM3 0x04000000
87#define CONFIG_SYS_IFC_CCR 0x01000000
88
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090089#ifdef CONFIG_MTD_NOR_FLASH
York Sun03017032015-03-20 19:28:23 -070090#define CONFIG_SYS_FLASH_QUIET_TEST
91#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
92
93#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
94#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
95#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
96#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
97
98#define CONFIG_SYS_FLASH_EMPTY_INFO
99#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
100 CONFIG_SYS_FLASH_BASE + 0x40000000}
101#endif
102
103#define CONFIG_NAND_FSL_IFC
104#define CONFIG_SYS_NAND_MAX_ECCPOS 256
105#define CONFIG_SYS_NAND_MAX_OOBFREE 2
106
York Sun03017032015-03-20 19:28:23 -0700107#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
108#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
109 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
110 | CSPR_MSEL_NAND /* MSEL = NAND */ \
111 | CSPR_V)
112#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
113
114#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
115 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
116 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
117 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
118 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
119 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
120 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
121
122#define CONFIG_SYS_NAND_ONFI_DETECTION
123
124/* ONFI NAND Flash mode0 Timing Params */
125#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
126 FTIM0_NAND_TWP(0x18) | \
127 FTIM0_NAND_TWCHT(0x07) | \
128 FTIM0_NAND_TWH(0x0a))
129#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
130 FTIM1_NAND_TWBE(0x39) | \
131 FTIM1_NAND_TRR(0x0e) | \
132 FTIM1_NAND_TRP(0x18))
133#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
134 FTIM2_NAND_TREH(0x0a) | \
135 FTIM2_NAND_TWHRE(0x1e))
136#define CONFIG_SYS_NAND_FTIM3 0x0
137
138#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
139#define CONFIG_SYS_MAX_NAND_DEVICE 1
140#define CONFIG_MTD_NAND_VERIFY_WRITE
York Sun03017032015-03-20 19:28:23 -0700141
142#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
143
144#define CONFIG_FSL_QIXIS /* use common QIXIS code */
145#define QIXIS_LBMAP_SWITCH 0x06
146#define QIXIS_LBMAP_MASK 0x0f
147#define QIXIS_LBMAP_SHIFT 0
148#define QIXIS_LBMAP_DFLTBANK 0x00
149#define QIXIS_LBMAP_ALTBANK 0x04
Scott Wood8e728cd2015-03-24 13:25:02 -0700150#define QIXIS_LBMAP_NAND 0x09
Santan Kumar1afa9002017-05-05 15:42:29 +0530151#define QIXIS_LBMAP_SD 0x00
Yuan Yao331c87c2016-06-08 18:25:00 +0800152#define QIXIS_LBMAP_QSPI 0x0f
York Sun03017032015-03-20 19:28:23 -0700153#define QIXIS_RST_CTL_RESET 0x31
154#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
155#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
156#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Scott Wood8e728cd2015-03-24 13:25:02 -0700157#define QIXIS_RCW_SRC_NAND 0x107
Santan Kumar1afa9002017-05-05 15:42:29 +0530158#define QIXIS_RCW_SRC_SD 0x40
Yuan Yao331c87c2016-06-08 18:25:00 +0800159#define QIXIS_RCW_SRC_QSPI 0x62
York Sun03017032015-03-20 19:28:23 -0700160#define QIXIS_RST_FORCE_MEM 0x01
161
162#define CONFIG_SYS_CSPR3_EXT (0x0)
163#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
164 | CSPR_PORT_SIZE_8 \
165 | CSPR_MSEL_GPCM \
166 | CSPR_V)
167#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
168 | CSPR_PORT_SIZE_8 \
169 | CSPR_MSEL_GPCM \
170 | CSPR_V)
171
172#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
173#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
174/* QIXIS Timing parameters for IFC CS3 */
175#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
176 FTIM0_GPCM_TEADC(0x0e) | \
177 FTIM0_GPCM_TEAHC(0x0e))
178#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
179 FTIM1_GPCM_TRAD(0x3f))
180#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
181 FTIM2_GPCM_TCH(0xf) | \
182 FTIM2_GPCM_TWP(0x3E))
183#define CONFIG_SYS_CS3_FTIM3 0x0
184
Santan Kumar99136482017-05-05 15:42:28 +0530185#if defined(CONFIG_SPL)
186#if defined(CONFIG_NAND_BOOT)
Scott Wood8e728cd2015-03-24 13:25:02 -0700187#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
188#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
189#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
190#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
191#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
192#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
193#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
194#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
195#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
196#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
197#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
198#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
199#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
200#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
201#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
202#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
203#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
204#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
205#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
206#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
207#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
208#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
209#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
210#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
211#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
212#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
213#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
214
Scott Wood8e728cd2015-03-24 13:25:02 -0700215#define CONFIG_SPL_PAD_TO 0x20000
216#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
Yuan Yao5d555b92016-06-08 18:24:58 +0800217#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
Santan Kumar99136482017-05-05 15:42:28 +0530218#endif
Scott Wood8e728cd2015-03-24 13:25:02 -0700219#else
York Sun03017032015-03-20 19:28:23 -0700220#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
221#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
222#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
223#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
224#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
225#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
226#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
227#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
228#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
229#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
230#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
231#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
232#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
233#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
234#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
235#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
236#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
237#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
238#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
239#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
240#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
241#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
242#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
243#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
244#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
245#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
246#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
Yuan Yao331c87c2016-06-08 18:25:00 +0800247#endif
Scott Wood8e728cd2015-03-24 13:25:02 -0700248
York Sun03017032015-03-20 19:28:23 -0700249/* Debug Server firmware */
250#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
251#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
252
York Sun03017032015-03-20 19:28:23 -0700253#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
254
255/*
256 * I2C
257 */
258#define I2C_MUX_PCA_ADDR 0x77
259#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
260
261/* I2C bus multiplexer */
262#define I2C_MUX_CH_DEFAULT 0x8
263
Haikun Wang9547c5d2015-07-03 16:51:34 +0800264/* SPI */
Yuan Yao6fc42b02016-06-08 18:24:55 +0800265#ifdef CONFIG_FSL_DSPI
266#define CONFIG_SPI_FLASH_STMICRO
267#define CONFIG_SPI_FLASH_SST
268#define CONFIG_SPI_FLASH_EON
269#endif
270
271#ifdef CONFIG_FSL_QSPI
272#define CONFIG_SPI_FLASH_SPANSION
Yuan Yao6fc42b02016-06-08 18:24:55 +0800273#endif
Yuan Yao86f42d72016-06-08 18:24:57 +0800274/*
275 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
276 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
277 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
278 */
279#define FSL_QIXIS_BRDCFG9_QSPI 0x1
Yuan Yao6fc42b02016-06-08 18:24:55 +0800280
York Sun03017032015-03-20 19:28:23 -0700281/*
Yangbo Lud0e295d2015-03-20 19:28:31 -0700282 * MMC
283 */
284#ifdef CONFIG_MMC
285#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
286 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
287#endif
288
289/*
York Sun03017032015-03-20 19:28:23 -0700290 * RTC configuration
291 */
292#define RTC
293#define CONFIG_RTC_DS3231 1
Chuanhua Han1ab68c72019-07-26 19:24:01 +0800294#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
York Sun03017032015-03-20 19:28:23 -0700295#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Chuanhua Han4f97aac2019-07-26 19:24:00 +0800296#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
York Sun03017032015-03-20 19:28:23 -0700297
298/* EEPROM */
York Sun03017032015-03-20 19:28:23 -0700299#define CONFIG_SYS_I2C_EEPROM_NXID
300#define CONFIG_SYS_EEPROM_BUS_NUM 0
York Sun03017032015-03-20 19:28:23 -0700301
York Sun03017032015-03-20 19:28:23 -0700302#define CONFIG_FSL_MEMAC
York Sun03017032015-03-20 19:28:23 -0700303
304#ifdef CONFIG_PCI
York Sun03017032015-03-20 19:28:23 -0700305#define CONFIG_PCI_SCAN_SHOW
York Sun03017032015-03-20 19:28:23 -0700306#endif
307
York Sun03017032015-03-20 19:28:23 -0700308/* Initial environment variables */
309#undef CONFIG_EXTRA_ENV_SETTINGS
Udit Agarwal22ec2382019-11-07 16:11:32 +0000310#ifdef CONFIG_NXP_ESBC
York Sun03017032015-03-20 19:28:23 -0700311#define CONFIG_EXTRA_ENV_SETTINGS \
312 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
313 "loadaddr=0x80100000\0" \
314 "kernel_addr=0x100000\0" \
315 "ramdisk_addr=0x800000\0" \
316 "ramdisk_size=0x2000000\0" \
317 "fdt_high=0xa0000000\0" \
318 "initrd_high=0xffffffffffffffff\0" \
Udit Agarwald11fed72017-05-02 17:43:57 +0530319 "kernel_start=0x581000000\0" \
York Sun03017032015-03-20 19:28:23 -0700320 "kernel_load=0xa0000000\0" \
Prabhakar Kushwahaae193f92016-02-03 17:03:51 +0530321 "kernel_size=0x2800000\0" \
Santan Kumar0a946f42017-02-06 14:18:12 +0530322 "mcmemsize=0x40000000\0" \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000323 "mcinitcmd=esbc_validate 0x580640000;" \
324 "esbc_validate 0x580680000;" \
Udit Agarwald11fed72017-05-02 17:43:57 +0530325 "fsl_mc start mc 0x580a00000" \
326 " 0x580e00000 \0"
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000327#else
328#ifdef CONFIG_TFABOOT
329#define SD_MC_INIT_CMD \
Priyanka Jainb20a9c72021-07-19 14:54:25 +0530330 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
Wasim Khan2260b3e2019-06-10 10:17:27 +0000331 "mmc read 0x80e00000 0x7000 0x800;" \
332 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000333#define IFC_MC_INIT_CMD \
334 "fsl_mc start mc 0x580a00000" \
335 " 0x580e00000 \0"
336#define CONFIG_EXTRA_ENV_SETTINGS \
337 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
338 "loadaddr=0x80100000\0" \
339 "loadaddr_sd=0x90100000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000340 "kernel_addr=0x581000000\0" \
341 "kernel_addr_sd=0x8000\0" \
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000342 "ramdisk_addr=0x800000\0" \
343 "ramdisk_size=0x2000000\0" \
344 "fdt_high=0xa0000000\0" \
345 "initrd_high=0xffffffffffffffff\0" \
346 "kernel_start=0x581000000\0" \
347 "kernel_start_sd=0x8000\0" \
348 "kernel_load=0xa0000000\0" \
349 "kernel_size=0x2800000\0" \
350 "kernel_size_sd=0x14000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000351 "load_addr=0xa0000000\0" \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000352 "kernelheader_addr=0x580600000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000353 "kernelheader_addr_r=0x80200000\0" \
354 "kernelheader_size=0x40000\0" \
355 "BOARD=ls2088aqds\0" \
356 "mcmemsize=0x70000000 \0" \
Biwen Li35c82d62020-03-19 20:01:07 +0800357 "scriptaddr=0x80000000\0" \
358 "scripthdraddr=0x80080000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000359 IFC_MC_INIT_CMD \
Biwen Li35c82d62020-03-19 20:01:07 +0800360 BOOTENV \
361 "boot_scripts=ls2088aqds_boot.scr\0" \
362 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
363 "scan_dev_for_boot_part=" \
364 "part list ${devtype} ${devnum} devplist; " \
365 "env exists devplist || setenv devplist 1; " \
366 "for distro_bootpart in ${devplist}; do " \
367 "if fstype ${devtype} " \
368 "${devnum}:${distro_bootpart} " \
369 "bootfstype; then " \
370 "run scan_dev_for_boot; " \
371 "fi; " \
372 "done\0" \
373 "boot_a_script=" \
374 "load ${devtype} ${devnum}:${distro_bootpart} " \
375 "${scriptaddr} ${prefix}${script}; " \
376 "env exists secureboot && load ${devtype} " \
377 "${devnum}:${distro_bootpart} " \
378 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
379 "&& esbc_validate ${scripthdraddr};" \
380 "source ${scriptaddr}\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000381 "nor_bootcmd=echo Trying load from nor..;" \
382 "cp.b $kernel_addr $load_addr " \
383 "$kernel_size ; env exists secureboot && " \
384 "cp.b $kernelheader_addr $kernelheader_addr_r " \
385 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
386 "bootm $load_addr#$BOARD\0" \
387 "sd_bootcmd=echo Trying load from SD ..;" \
388 "mmcinfo; mmc read $load_addr " \
389 "$kernel_addr_sd $kernel_size_sd && " \
390 "bootm $load_addr#$BOARD\0"
Santan Kumar1afa9002017-05-05 15:42:29 +0530391#elif defined(CONFIG_SD_BOOT)
392#define CONFIG_EXTRA_ENV_SETTINGS \
393 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
394 "loadaddr=0x90100000\0" \
395 "kernel_addr=0x800\0" \
396 "ramdisk_addr=0x800000\0" \
397 "ramdisk_size=0x2000000\0" \
398 "fdt_high=0xa0000000\0" \
399 "initrd_high=0xffffffffffffffff\0" \
400 "kernel_start=0x8000\0" \
401 "kernel_load=0xa0000000\0" \
402 "kernel_size=0x14000\0" \
Priyanka Jainb20a9c72021-07-19 14:54:25 +0530403 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
404 "mmc read 0x80e00000 0x7000 0x800;" \
405 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
Santan Kumar1afa9002017-05-05 15:42:29 +0530406 "mcmemsize=0x70000000 \0"
Udit Agarwal18583432017-01-06 15:58:57 +0530407#else
408#define CONFIG_EXTRA_ENV_SETTINGS \
409 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
410 "loadaddr=0x80100000\0" \
411 "kernel_addr=0x100000\0" \
412 "ramdisk_addr=0x800000\0" \
413 "ramdisk_size=0x2000000\0" \
414 "fdt_high=0xa0000000\0" \
415 "initrd_high=0xffffffffffffffff\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530416 "kernel_start=0x581000000\0" \
Udit Agarwal18583432017-01-06 15:58:57 +0530417 "kernel_load=0xa0000000\0" \
418 "kernel_size=0x2800000\0" \
Santan Kumar0a946f42017-02-06 14:18:12 +0530419 "mcmemsize=0x40000000\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530420 "mcinitcmd=fsl_mc start mc 0x580a00000" \
421 " 0x580e00000 \0"
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000422#endif /* CONFIG_TFABOOT */
Udit Agarwal22ec2382019-11-07 16:11:32 +0000423#endif /* CONFIG_NXP_ESBC */
Udit Agarwal18583432017-01-06 15:58:57 +0530424
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000425#ifdef CONFIG_TFABOOT
Biwen Li35c82d62020-03-19 20:01:07 +0800426#define BOOT_TARGET_DEVICES(func) \
427 func(USB, usb, 0) \
428 func(MMC, mmc, 0) \
429 func(SCSI, scsi, 0) \
430 func(DHCP, dhcp, na)
431#include <config_distro_bootcmd.h>
432
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000433#define SD_BOOTCOMMAND \
434 "env exists mcinitcmd && env exists secureboot "\
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000435 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000436 "&& esbc_validate $load_addr; " \
437 "env exists mcinitcmd && run mcinitcmd " \
Wasim Khan2260b3e2019-06-10 10:17:27 +0000438 "&& mmc read 0x80d00000 0x6800 0x800 " \
439 "&& fsl_mc lazyapply dpl 0x80d00000; " \
Biwen Li35c82d62020-03-19 20:01:07 +0800440 "run distro_bootcmd;run sd_bootcmd; " \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000441 "env exists secureboot && esbc_halt;"
442
443#define IFC_NOR_BOOTCOMMAND \
444 "env exists mcinitcmd && env exists secureboot "\
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000445 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000446 "&& fsl_mc lazyapply dpl 0x580d00000;" \
Biwen Li35c82d62020-03-19 20:01:07 +0800447 "run distro_bootcmd;run nor_bootcmd; " \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000448 "env exists secureboot && esbc_halt;"
449#endif
450
Santan Kumar1afa9002017-05-05 15:42:29 +0530451#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
Prabhakar Kushwahac158fad2015-03-20 19:28:26 -0700452#define CONFIG_FSL_MEMAC
Prabhakar Kushwahac158fad2015-03-20 19:28:26 -0700453#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
454#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
455#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
456#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
457
Prabhakar Kushwaha35f93f62015-08-07 18:01:51 +0530458#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
459#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
460#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
461#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
462#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
463#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
464#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
465#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
466#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
467#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
468#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
469#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
470#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
471#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
472#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
473#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
474
Prabhakar Kushwaha0a95f8f2016-04-19 08:53:42 +0530475#define CONFIG_ETHPRIME "DPMAC1@xgmii"
Prabhakar Kushwahac158fad2015-03-20 19:28:26 -0700476
477#endif
478
Saksham Jainc0c38d22016-03-23 16:24:35 +0530479#include <asm/fsl_secure_boot.h>
480
York Sun03017032015-03-20 19:28:23 -0700481#endif /* __LS2_QDS_H */