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git01.mediatek.com / filogic / uboot / 3fb25406ec70aca3f1dc85032e561cf5784bf714 / . / doc / board / xilinx / zynqmp-r5.rst
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Michal Simek9fb6eed2020-09-14 15:00:06 +0200[diff] [blame]1.. SPDX-License-Identifier: GPL-2.0
2.. (C) Copyright 2020 Xilinx, Inc.
3
4ZYNQMP-R5
5=========
6
7About this
8----------
9
10This document describes the information about Xilinx Zynq UltraScale+ MPSOC
11U-Boot Cortex R5 support.
12
13ZynqMP R5 boards
14----------------
15
16* zynqmp-r5 - U-Boot running on RPU Cortex-R5
17
18Building
19--------
20
21configure and build armv7 toolchain::
22
23 $ make xilinx_zynqmp_r5_defconfig
24 $ make
25
26Notes
27^^^^^
28
29Output fragment is u-boot.
30
31Loading
32-------
33
34ZynqMP R5 U-Boot was created for supporting loading OS on RPU. There are two
35ways how to start U-Boot on R5.
36
37Bootgen
38^^^^^^^
39
40The first way is to use Xilinx FSBL (First stage
41bootloader) to load u-boot and start it. The following bif can be used for boot
42image generation via Xilinx bootgen utility::
43
44
45 the_ROM_image:
46 {
47 [bootloader,destination_cpu=r5-0] fsbl_rpu.elf
48 [destination_cpu=r5-0]u-boot.elf
49 }
50
51Bootgen command for building boot.bin::
52
53 bootgen -image <bif>.bif -r -w -o i boot.bin
54
55
56U-Boot cpu command
57^^^^^^^^^^^^^^^^^^
58
59The second way to load U-Boot to Cortex R5 is from U-Boot running on A53 as is
60visible from the following log::
61
62 U-Boot SPL 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
63 PMUFW: v1.1
64 Loading new PMUFW cfg obj (2024 bytes)
65 EL Level: EL3
66 Multiboot: 0
67 Trying to boot from MMC2
68 spl: could not initialize mmc. error: -19
69 Trying to boot from MMC1
70 spl_load_image_fat_os: error reading image u-boot.bin, err - -2
71 NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000
72 NOTICE: BL31: v2.2(release):v2.2-614-ged9dc512fb9c
73 NOTICE: BL31: Built : 09:32:09, Mar 13 2020
74
75
76 U-Boot 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
77
78 Model: ZynqMP ZCU104 RevC
79 Board: Xilinx ZynqMP
80 DRAM: 2 GiB
81 PMUFW: v1.1
82 EL Level: EL2
83 Chip ID: zu7e
84 WDT: Started with servicing (60s timeout)
85 NAND: 0 MiB
86 MMC: mmc@ff170000: 0
87 Loading Environment from FAT... *** Warning - bad CRC, using default environment
88
89 In: serial
90 Out: serial
91 Err: serial
92 Bootmode: LVL_SHFT_SD_MODE1
93 Reset reason: SOFT
94 Net:
95 ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id
96 eth0: ethernet@ff0e0000
97 Hit any key to stop autoboot: 0
98 ZynqMP> setenv autoload no
99 ZynqMP> dhcp
100 BOOTP broadcast 1
101 DHCP client bound to address 192.168.0.167 (8 ms)
102 ZynqMP> tftpboot 20000000 192.168.0.105:u-boot-r5-2.elf
103 Using ethernet@ff0e0000 device
104 TFTP from server 192.168.0.105; our IP address is 192.168.0.167
105 Filename 'u-boot-r5-2.elf'.
106 Load address: 0x20000000
107 Loading: #################################################################
108 #################################################################
109 #################################################################
110 #################################################################
111 #################################################################
112 #################################################################
113 ################
114 376 KiB/s
115 done
116 Bytes transferred = 2075464 (1fab48 hex)
117 ZynqMP> setenv autostart no
118 ZynqMP> bootelf -p 20000000
119 ZynqMP> cpu 4 release 10000000 lockstep
120 Using TCM jump trampoline for address 0x10000000
121 R5 lockstep mode
122 ZynqMP>
123
124Then on second uart you can see U-Boot up and running on R5::
125
126 U-Boot 2020.10-rc4-00071-g7045622cc9ba (Sep 16 2020 - 13:38:53 +0200)
127
128 Model: Xilinx ZynqMP R5
129 DRAM: 512 MiB
130 MMC:
131 In: serial@ff010000
132 Out: serial@ff010000
133 Err: serial@ff010000
134 Net: No ethernet found.
135 ZynqMP r5>
136
137Please make sure MIO pins for uart are properly configured to see output.