Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 3fab9dc4bca1fbbc14cc7ef86288e0b261298dd8 / . / arch / xtensa / include / asm / arch-dc233c / tie-asm.h
blob: 7b3d1f3c57251a12846ebafe9c20f81aab10b738 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Max Filippovcd3a80d2016-08-10 18:36:46 +0300[diff] [blame]2/*
3 * This header file contains assembly-language definitions (assembly
4 * macros, etc.) for this specific Xtensa processor's TIE extensions
5 * and options. It is customized to this Xtensa processor configuration.
6 * This file is autogenerated, please do not edit.
7 *
8 * Copyright (C) 1999-2010 Tensilica Inc.
Max Filippovcd3a80d2016-08-10 18:36:46 +0300[diff] [blame]9 */
10
11#ifndef _XTENSA_CORE_TIE_ASM_H
12#define _XTENSA_CORE_TIE_ASM_H
13
14/* Selection parameter values for save-area save/restore macros: */
15/* Option vs. TIE: */
16#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
17#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
18#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
19/* Whether used automatically by compiler: */
20#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
21#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
22#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
28/* Misc */
29#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
30#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
31 | ((ccuse) & XTHAL_SAS_ANYCC) \
32 | ((abi) & XTHAL_SAS_ANYABI) )
33
Max Filippovcd3a80d2016-08-10 18:36:46 +0300[diff] [blame]34 /*
35 * Macro to save all non-coprocessor (extra) custom TIE and optional state
36 * (not including zero-overhead loop registers).
37 * Required parameters:
38 * ptr Save area pointer address register (clobbered)
39 * (register must contain a 4 byte aligned address).
40 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
41 * registers are clobbered, the remaining are unused).
42 * Optional parameters:
43 * continue If macro invoked as part of a larger store sequence, set to 1
44 * if this is not the first in the sequence. Defaults to 0.
45 * ofs Offset from start of larger sequence (from value of first ptr
46 * in sequence) at which to store. Defaults to next available space
47 * (or 0 if <continue> is 0).
48 * select Select what category(ies) of registers to store, as a bitmask
49 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
50 * alloc Select what category(ies) of registers to allocate; if any
51 * category is selected here that is not in <select>, space for
52 * the corresponding registers is skipped without doing any store.
53 */
54 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
55 xchal_sa_start \continue, \ofs
56 // Optional global register used by default by the compiler:
57 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
58 xchal_sa_align \ptr, 0, 1020, 4, 4
59 rur.THREADPTR \at1 // threadptr option
60 s32i \at1, \ptr, .Lxchal_ofs_+0
61 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
62 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
63 xchal_sa_align \ptr, 0, 1020, 4, 4
64 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
65 .endif
66 // Optional caller-saved registers used by default by the compiler:
67 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
68 xchal_sa_align \ptr, 0, 1016, 4, 4
69 rsr \at1, ACCLO // MAC16 option
70 s32i \at1, \ptr, .Lxchal_ofs_+0
71 rsr \at1, ACCHI // MAC16 option
72 s32i \at1, \ptr, .Lxchal_ofs_+4
73 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
74 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
75 xchal_sa_align \ptr, 0, 1016, 4, 4
76 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
77 .endif
78 // Optional caller-saved registers not used by default by the compiler:
79 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
80 xchal_sa_align \ptr, 0, 1004, 4, 4
81 rsr \at1, M0 // MAC16 option
82 s32i \at1, \ptr, .Lxchal_ofs_+0
83 rsr \at1, M1 // MAC16 option
84 s32i \at1, \ptr, .Lxchal_ofs_+4
85 rsr \at1, M2 // MAC16 option
86 s32i \at1, \ptr, .Lxchal_ofs_+8
87 rsr \at1, M3 // MAC16 option
88 s32i \at1, \ptr, .Lxchal_ofs_+12
89 rsr \at1, SCOMPARE1 // conditional store option
90 s32i \at1, \ptr, .Lxchal_ofs_+16
91 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
92 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
93 xchal_sa_align \ptr, 0, 1004, 4, 4
94 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
95 .endif
96 .endm // xchal_ncp_store
97
98 /*
99 * Macro to restore all non-coprocessor (extra) custom TIE and optional state
100 * (not including zero-overhead loop registers).
101 * Required parameters:
102 * ptr Save area pointer address register (clobbered)
103 * (register must contain a 4 byte aligned address).
104 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
105 * registers are clobbered, the remaining are unused).
106 * Optional parameters:
107 * continue If macro invoked as part of a larger load sequence, set to 1
108 * if this is not the first in the sequence. Defaults to 0.
109 * ofs Offset from start of larger sequence (from value of first ptr
110 * in sequence) at which to load. Defaults to next available space
111 * (or 0 if <continue> is 0).
112 * select Select what category(ies) of registers to load, as a bitmask
113 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
114 * alloc Select what category(ies) of registers to allocate; if any
115 * category is selected here that is not in <select>, space for
116 * the corresponding registers is skipped without doing any load.
117 */
118 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
119 xchal_sa_start \continue, \ofs
120 // Optional global register used by default by the compiler:
121 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
122 xchal_sa_align \ptr, 0, 1020, 4, 4
123 l32i \at1, \ptr, .Lxchal_ofs_+0
124 wur.THREADPTR \at1 // threadptr option
125 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
126 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
127 xchal_sa_align \ptr, 0, 1020, 4, 4
128 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
129 .endif
130 // Optional caller-saved registers used by default by the compiler:
131 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
132 xchal_sa_align \ptr, 0, 1016, 4, 4
133 l32i \at1, \ptr, .Lxchal_ofs_+0
134 wsr \at1, ACCLO // MAC16 option
135 l32i \at1, \ptr, .Lxchal_ofs_+4
136 wsr \at1, ACCHI // MAC16 option
137 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
138 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
139 xchal_sa_align \ptr, 0, 1016, 4, 4
140 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
141 .endif
142 // Optional caller-saved registers not used by default by the compiler:
143 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
144 xchal_sa_align \ptr, 0, 1004, 4, 4
145 l32i \at1, \ptr, .Lxchal_ofs_+0
146 wsr \at1, M0 // MAC16 option
147 l32i \at1, \ptr, .Lxchal_ofs_+4
148 wsr \at1, M1 // MAC16 option
149 l32i \at1, \ptr, .Lxchal_ofs_+8
150 wsr \at1, M2 // MAC16 option
151 l32i \at1, \ptr, .Lxchal_ofs_+12
152 wsr \at1, M3 // MAC16 option
153 l32i \at1, \ptr, .Lxchal_ofs_+16
154 wsr \at1, SCOMPARE1 // conditional store option
155 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
156 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
157 xchal_sa_align \ptr, 0, 1004, 4, 4
158 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
159 .endif
160 .endm // xchal_ncp_load
161
162
163#define XCHAL_NCP_NUM_ATMPS 1
164
Max Filippovcd3a80d2016-08-10 18:36:46 +0300[diff] [blame]165#define XCHAL_SA_NUM_ATMPS 1
166
167#endif /*_XTENSA_CORE_TIE_ASM_H*/