blob: a42a7e6bbd65a90b813f6741d5aee7e4a4d963ac [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Saket Sinha331141a2015-08-22 12:20:55 +05302/*
3 * Based on acpi.c from coreboot
4 *
5 * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
Bin Meng44256b02016-05-07 07:46:25 -07006 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
Saket Sinha331141a2015-08-22 12:20:55 +05307 */
8
Simon Glass2326a8b2020-09-22 12:45:34 -06009#define LOG_CATEGORY LOGC_ACPI
10
Simon Glass272a7032020-09-22 12:45:32 -060011#include <bloblist.h>
Saket Sinha331141a2015-08-22 12:20:55 +053012#include <cpu.h>
13#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Saket Sinha331141a2015-08-22 12:20:55 +053015#include <dm/uclass-internal.h>
Simon Glass0e113842020-04-26 09:19:47 -060016#include <mapmem.h>
Andy Shevchenko4ca48c92018-11-20 23:52:38 +020017#include <serial.h>
Simon Glassf0a8d682020-07-07 13:12:07 -060018#include <acpi/acpigen.h>
Simon Glass95971892020-09-22 12:45:10 -060019#include <acpi/acpi_device.h>
Simon Glass858fed12020-04-08 16:57:36 -060020#include <acpi/acpi_table.h>
Bin Mengd9050c62016-06-17 02:13:16 -070021#include <asm/acpi/global_nvs.h>
Andy Shevchenko13a5d872017-07-21 22:32:04 +030022#include <asm/ioapic.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060023#include <asm/global_data.h>
Saket Sinha331141a2015-08-22 12:20:55 +053024#include <asm/lapic.h>
Andy Shevchenko13a5d872017-07-21 22:32:04 +030025#include <asm/mpspec.h>
Saket Sinha331141a2015-08-22 12:20:55 +053026#include <asm/tables.h>
Bin Mengd9050c62016-06-17 02:13:16 -070027#include <asm/arch/global_nvs.h>
Simon Glass0e113842020-04-26 09:19:47 -060028#include <dm/acpi.h>
Simon Glass9ed41e72020-07-07 21:32:05 -060029#include <linux/err.h>
Saket Sinha331141a2015-08-22 12:20:55 +053030
Saket Sinha331141a2015-08-22 12:20:55 +053031static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
Bin Meng44256b02016-05-07 07:46:25 -070032 u8 cpu, u8 apic)
Saket Sinha331141a2015-08-22 12:20:55 +053033{
Bin Meng44256b02016-05-07 07:46:25 -070034 lapic->type = ACPI_APIC_LAPIC;
Saket Sinha331141a2015-08-22 12:20:55 +053035 lapic->length = sizeof(struct acpi_madt_lapic);
Bin Meng44256b02016-05-07 07:46:25 -070036 lapic->flags = LOCAL_APIC_FLAG_ENABLED;
Saket Sinha331141a2015-08-22 12:20:55 +053037 lapic->processor_id = cpu;
38 lapic->apic_id = apic;
39
40 return lapic->length;
41}
42
Bin Meng3c5234e2016-05-07 07:46:30 -070043int acpi_create_madt_lapics(u32 current)
Saket Sinha331141a2015-08-22 12:20:55 +053044{
45 struct udevice *dev;
George McCollister5a49f872016-06-07 13:40:18 -050046 int total_length = 0;
Simon Glassfcae5472020-09-22 12:45:31 -060047 int cpu_num = 0;
Saket Sinha331141a2015-08-22 12:20:55 +053048
49 for (uclass_find_first_device(UCLASS_CPU, &dev);
50 dev;
51 uclass_find_next_device(&dev)) {
Simon Glassb75b15b2020-12-03 16:55:23 -070052 struct cpu_plat *plat = dev_get_parent_plat(dev);
Simon Glassfcae5472020-09-22 12:45:31 -060053 int length;
54
55 length = acpi_create_madt_lapic(
56 (struct acpi_madt_lapic *)current, cpu_num++,
57 plat->cpu_id);
Bin Meng3c5234e2016-05-07 07:46:30 -070058 current += length;
George McCollister5a49f872016-06-07 13:40:18 -050059 total_length += length;
Bin Meng44256b02016-05-07 07:46:25 -070060 }
61
George McCollister5a49f872016-06-07 13:40:18 -050062 return total_length;
Saket Sinha331141a2015-08-22 12:20:55 +053063}
64
Bin Meng44256b02016-05-07 07:46:25 -070065int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
66 u32 addr, u32 gsi_base)
Saket Sinha331141a2015-08-22 12:20:55 +053067{
Bin Meng6a421582016-05-07 07:46:21 -070068 ioapic->type = ACPI_APIC_IOAPIC;
Saket Sinha331141a2015-08-22 12:20:55 +053069 ioapic->length = sizeof(struct acpi_madt_ioapic);
70 ioapic->reserved = 0x00;
71 ioapic->gsi_base = gsi_base;
72 ioapic->ioapic_id = id;
73 ioapic->ioapic_addr = addr;
74
75 return ioapic->length;
76}
77
78int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
Bin Meng44256b02016-05-07 07:46:25 -070079 u8 bus, u8 source, u32 gsirq, u16 flags)
Saket Sinha331141a2015-08-22 12:20:55 +053080{
Bin Meng6a421582016-05-07 07:46:21 -070081 irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
Saket Sinha331141a2015-08-22 12:20:55 +053082 irqoverride->length = sizeof(struct acpi_madt_irqoverride);
83 irqoverride->bus = bus;
84 irqoverride->source = source;
85 irqoverride->gsirq = gsirq;
86 irqoverride->flags = flags;
87
88 return irqoverride->length;
89}
90
91int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
Bin Meng44256b02016-05-07 07:46:25 -070092 u8 cpu, u16 flags, u8 lint)
Saket Sinha331141a2015-08-22 12:20:55 +053093{
Bin Meng6a421582016-05-07 07:46:21 -070094 lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
Saket Sinha331141a2015-08-22 12:20:55 +053095 lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
96 lapic_nmi->flags = flags;
97 lapic_nmi->processor_id = cpu;
98 lapic_nmi->lint = lint;
99
100 return lapic_nmi->length;
101}
102
Andy Shevchenko13a5d872017-07-21 22:32:04 +0300103static int acpi_create_madt_irq_overrides(u32 current)
104{
105 struct acpi_madt_irqoverride *irqovr;
106 u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
107 int length = 0;
108
109 irqovr = (void *)current;
110 length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
111
112 irqovr = (void *)(current + length);
113 length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
114
115 return length;
116}
117
118__weak u32 acpi_fill_madt(u32 current)
119{
120 current += acpi_create_madt_lapics(current);
121
122 current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
123 io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
124
125 current += acpi_create_madt_irq_overrides(current);
126
127 return current;
128}
129
Simon Glassb0d5fab2021-12-01 09:02:58 -0700130int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
Saket Sinha331141a2015-08-22 12:20:55 +0530131{
Simon Glassb0d5fab2021-12-01 09:02:58 -0700132 struct acpi_table_header *header;
133 struct acpi_madt *madt;
134 u32 current;
Saket Sinha331141a2015-08-22 12:20:55 +0530135
Simon Glassb0d5fab2021-12-01 09:02:58 -0700136 madt = ctx->current;
137
138 memset(madt, '\0', sizeof(struct acpi_madt));
139 header = &madt->header;
Saket Sinha331141a2015-08-22 12:20:55 +0530140
141 /* Fill out header fields */
Bin Mengb063d5f2016-05-07 07:46:24 -0700142 acpi_fill_header(header, "APIC");
Saket Sinha331141a2015-08-22 12:20:55 +0530143 header->length = sizeof(struct acpi_madt);
Simon Glassf3694aa2020-07-16 21:22:37 -0600144 header->revision = ACPI_MADT_REV_ACPI_3_0;
Saket Sinha331141a2015-08-22 12:20:55 +0530145
146 madt->lapic_addr = LAPIC_DEFAULT_BASE;
Bin Meng6a421582016-05-07 07:46:21 -0700147 madt->flags = ACPI_MADT_PCAT_COMPAT;
Saket Sinha331141a2015-08-22 12:20:55 +0530148
Simon Glassb0d5fab2021-12-01 09:02:58 -0700149 current = (u32)madt + sizeof(struct acpi_madt);
Saket Sinha331141a2015-08-22 12:20:55 +0530150 current = acpi_fill_madt(current);
151
152 /* (Re)calculate length and checksum */
Bin Menga1ec7db2016-05-07 07:46:26 -0700153 header->length = current - (u32)madt;
Saket Sinha331141a2015-08-22 12:20:55 +0530154
155 header->checksum = table_compute_checksum((void *)madt, header->length);
Simon Glassb0d5fab2021-12-01 09:02:58 -0700156 acpi_add_table(ctx, madt);
157 acpi_inc(ctx, madt->header.length);
158
159 return 0;
Saket Sinha331141a2015-08-22 12:20:55 +0530160}
Simon Glassb0d5fab2021-12-01 09:02:58 -0700161ACPI_WRITER(5x86, NULL, acpi_write_madt, 0);
Saket Sinha331141a2015-08-22 12:20:55 +0530162
Simon Glass28026282020-09-22 12:45:33 -0600163/**
164 * acpi_create_tcpa() - Create a TCPA table
165 *
Simon Glass28026282020-09-22 12:45:33 -0600166 * Trusted Computing Platform Alliance Capabilities Table
167 * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
168 * Firmware Specification 3.0
169 */
Simon Glassbb3b6082021-12-01 09:02:59 -0700170int acpi_write_tcpa(struct acpi_ctx *ctx, const struct acpi_writer *entry)
Simon Glass28026282020-09-22 12:45:33 -0600171{
Simon Glassbb3b6082021-12-01 09:02:59 -0700172 struct acpi_table_header *header;
173 struct acpi_tcpa *tcpa;
174 u32 current;
Simon Glass28026282020-09-22 12:45:33 -0600175 int size = 0x10000; /* Use this as the default size */
176 void *log;
177 int ret;
178
Simon Glassbb3b6082021-12-01 09:02:59 -0700179 if (!IS_ENABLED(CONFIG_TPM_V1))
180 return -ENOENT;
Simon Glass28026282020-09-22 12:45:33 -0600181 if (!CONFIG_IS_ENABLED(BLOBLIST))
182 return -ENXIO;
Simon Glassbb3b6082021-12-01 09:02:59 -0700183
184 tcpa = ctx->current;
185 header = &tcpa->header;
Simon Glass28026282020-09-22 12:45:33 -0600186 memset(tcpa, '\0', sizeof(struct acpi_tcpa));
187
188 /* Fill out header fields */
189 acpi_fill_header(header, "TCPA");
190 header->length = sizeof(struct acpi_tcpa);
191 header->revision = 1;
192
193 ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log);
194 if (ret)
195 return log_msg_ret("blob", ret);
196
197 tcpa->platform_class = 0;
198 tcpa->laml = size;
Simon Glass919f8352023-12-31 08:25:54 -0700199 tcpa->lasa = nomap_to_sysmem(log);
Simon Glass28026282020-09-22 12:45:33 -0600200
201 /* (Re)calculate length and checksum */
Simon Glassbb3b6082021-12-01 09:02:59 -0700202 current = (u32)tcpa + sizeof(struct acpi_tcpa);
Simon Glass28026282020-09-22 12:45:33 -0600203 header->length = current - (u32)tcpa;
Simon Glassbb3b6082021-12-01 09:02:59 -0700204 header->checksum = table_compute_checksum(tcpa, header->length);
205
206 acpi_inc(ctx, tcpa->header.length);
207 acpi_add_table(ctx, tcpa);
Simon Glass28026282020-09-22 12:45:33 -0600208
209 return 0;
210}
Simon Glassbb3b6082021-12-01 09:02:59 -0700211ACPI_WRITER(5tcpa, "TCPA", acpi_write_tcpa, 0);
Simon Glass28026282020-09-22 12:45:33 -0600212
Simon Glass272a7032020-09-22 12:45:32 -0600213static int get_tpm2_log(void **ptrp, int *sizep)
214{
215 const int tpm2_default_log_len = 0x10000;
216 int size;
217 int ret;
218
219 *sizep = 0;
220 size = tpm2_default_log_len;
221 ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp);
222 if (ret)
223 return log_msg_ret("blob", ret);
224 *sizep = size;
225
226 return 0;
227}
228
Simon Glassc7536942021-12-01 09:02:57 -0700229static int acpi_write_tpm2(struct acpi_ctx *ctx,
230 const struct acpi_writer *entry)
Simon Glass272a7032020-09-22 12:45:32 -0600231{
Simon Glassc7536942021-12-01 09:02:57 -0700232 struct acpi_table_header *header;
233 struct acpi_tpm2 *tpm2;
Simon Glass272a7032020-09-22 12:45:32 -0600234 int tpm2_log_len;
235 void *lasa;
236 int ret;
237
Simon Glassc7536942021-12-01 09:02:57 -0700238 if (!IS_ENABLED(CONFIG_TPM_V2))
239 return log_msg_ret("none", -ENOENT);
240
241 tpm2 = ctx->current;
242 header = &tpm2->header;
243 memset(tpm2, '\0', sizeof(struct acpi_tpm2));
Simon Glass272a7032020-09-22 12:45:32 -0600244
245 /*
246 * Some payloads like SeaBIOS depend on log area to use TPM2.
247 * Get the memory size and address of TPM2 log area or initialize it.
248 */
249 ret = get_tpm2_log(&lasa, &tpm2_log_len);
250 if (ret)
Simon Glassc7536942021-12-01 09:02:57 -0700251 return log_msg_ret("log", ret);
Simon Glass272a7032020-09-22 12:45:32 -0600252
253 /* Fill out header fields. */
254 acpi_fill_header(header, "TPM2");
Heinrich Schuchardt10de8a82024-01-21 12:52:48 +0100255 memcpy(header->creator_id, ASLC_ID, 4);
Simon Glass272a7032020-09-22 12:45:32 -0600256
257 header->length = sizeof(struct acpi_tpm2);
258 header->revision = acpi_get_table_revision(ACPITAB_TPM2);
259
Simon Glassc7536942021-12-01 09:02:57 -0700260 /* Hard to detect for U-Boot. Just set it to 0 */
Simon Glass272a7032020-09-22 12:45:32 -0600261 tpm2->platform_class = 0;
262
263 /* Must be set to 0 for FIFO-interface support */
264 tpm2->control_area = 0;
265 tpm2->start_method = 6;
266 memset(tpm2->msp, 0, sizeof(tpm2->msp));
267
268 /* Fill the log area size and start address fields. */
269 tpm2->laml = tpm2_log_len;
Simon Glass919f8352023-12-31 08:25:54 -0700270 tpm2->lasa = nomap_to_sysmem(lasa);
Simon Glass272a7032020-09-22 12:45:32 -0600271
272 /* Calculate checksum. */
Simon Glassc7536942021-12-01 09:02:57 -0700273 header->checksum = table_compute_checksum(tpm2, header->length);
274
275 acpi_inc(ctx, tpm2->header.length);
276 acpi_add_table(ctx, tpm2);
Simon Glass272a7032020-09-22 12:45:32 -0600277
278 return 0;
279}
Simon Glassc7536942021-12-01 09:02:57 -0700280ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0);
Simon Glass272a7032020-09-22 12:45:32 -0600281
Simon Glass6e6bc9b2021-12-01 09:03:00 -0700282int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
Andy Shevchenko607dbd12019-07-14 19:23:57 +0300283{
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200284 struct serial_device_info serial_info = {0};
285 ulong serial_address, serial_offset;
Simon Glass6e6bc9b2021-12-01 09:03:00 -0700286 struct acpi_table_header *header;
287 struct acpi_spcr *spcr;
Simon Glassdaaff932018-12-28 14:23:08 -0700288 struct udevice *dev;
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200289 uint serial_config;
290 uint serial_width;
291 int access_size;
292 int space_id;
Andy Shevchenkobf9c8e32019-02-28 17:19:54 +0200293 int ret = -ENODEV;
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200294
Simon Glass6e6bc9b2021-12-01 09:03:00 -0700295 spcr = ctx->current;
296 header = &spcr->header;
297
298 memset(spcr, '\0', sizeof(struct acpi_spcr));
Wolfgang Wallner13c23e92020-09-16 16:57:53 +0200299
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200300 /* Fill out header fields */
301 acpi_fill_header(header, "SPCR");
302 header->length = sizeof(struct acpi_spcr);
303 header->revision = 2;
304
Simon Glass896c1642018-12-28 14:23:10 -0700305 /* Read the device once, here. It is reused below */
Andy Shevchenkobf9c8e32019-02-28 17:19:54 +0200306 dev = gd->cur_serial_dev;
307 if (dev)
Simon Glass896c1642018-12-28 14:23:10 -0700308 ret = serial_getinfo(dev, &serial_info);
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200309 if (ret)
310 serial_info.type = SERIAL_CHIP_UNKNOWN;
311
312 /* Encode chip type */
313 switch (serial_info.type) {
314 case SERIAL_CHIP_16550_COMPATIBLE:
315 spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
316 break;
317 case SERIAL_CHIP_UNKNOWN:
318 default:
319 spcr->interface_type = ACPI_DBG2_UNKNOWN;
320 break;
321 }
322
323 /* Encode address space */
324 switch (serial_info.addr_space) {
325 case SERIAL_ADDRESS_SPACE_MEMORY:
326 space_id = ACPI_ADDRESS_SPACE_MEMORY;
327 break;
328 case SERIAL_ADDRESS_SPACE_IO:
329 default:
330 space_id = ACPI_ADDRESS_SPACE_IO;
331 break;
332 }
333
334 serial_width = serial_info.reg_width * 8;
335 serial_offset = serial_info.reg_offset << serial_info.reg_shift;
336 serial_address = serial_info.addr + serial_offset;
337
338 /* Encode register access size */
339 switch (serial_info.reg_shift) {
340 case 0:
341 access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
342 break;
343 case 1:
344 access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
345 break;
346 case 2:
347 access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
348 break;
349 case 3:
350 access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
351 break;
352 default:
353 access_size = ACPI_ACCESS_SIZE_UNDEFINED;
354 break;
355 }
356
357 debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
358
359 /* Fill GAS */
360 spcr->serial_port.space_id = space_id;
361 spcr->serial_port.bit_width = serial_width;
362 spcr->serial_port.bit_offset = 0;
363 spcr->serial_port.access_size = access_size;
364 spcr->serial_port.addrl = lower_32_bits(serial_address);
365 spcr->serial_port.addrh = upper_32_bits(serial_address);
366
367 /* Encode baud rate */
368 switch (serial_info.baudrate) {
369 case 9600:
370 spcr->baud_rate = 3;
371 break;
372 case 19200:
373 spcr->baud_rate = 4;
374 break;
375 case 57600:
376 spcr->baud_rate = 6;
377 break;
378 case 115200:
379 spcr->baud_rate = 7;
380 break;
381 default:
382 spcr->baud_rate = 0;
383 break;
384 }
385
Simon Glass896c1642018-12-28 14:23:10 -0700386 serial_config = SERIAL_DEFAULT_CONFIG;
387 if (dev)
Simon Glassdaaff932018-12-28 14:23:08 -0700388 ret = serial_getconfig(dev, &serial_config);
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200389
390 spcr->parity = SERIAL_GET_PARITY(serial_config);
391 spcr->stop_bits = SERIAL_GET_STOP(serial_config);
392
393 /* No PCI devices for now */
394 spcr->pci_device_id = 0xffff;
395 spcr->pci_vendor_id = 0xffff;
396
Andy Shevchenko225cc8a2020-02-27 17:21:56 +0200397 /*
398 * SPCR has no clue if the UART base clock speed is different
399 * to the default one. However, the SPCR 1.04 defines baud rate
400 * 0 as a preconfigured state of UART and OS is supposed not
401 * to touch the configuration of the serial device.
402 */
403 if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
404 spcr->baud_rate = 0;
405
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200406 /* Fix checksum */
407 header->checksum = table_compute_checksum((void *)spcr, header->length);
Simon Glass6e6bc9b2021-12-01 09:03:00 -0700408
409 acpi_add_table(ctx, spcr);
410 acpi_inc(ctx, spcr->header.length);
411
412 return 0;
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200413}
Simon Glass6e6bc9b2021-12-01 09:03:00 -0700414ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
Andy Shevchenko4ca48c92018-11-20 23:52:38 +0200415
Simon Glassd2a98eb2021-12-01 09:02:53 -0700416int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
Saket Sinha331141a2015-08-22 12:20:55 +0530417{
Simon Glass0e113842020-04-26 09:19:47 -0600418 ulong addr;
Saket Sinha331141a2015-08-22 12:20:55 +0530419
Simon Glass6fe570a2020-09-22 12:44:53 -0600420 if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
Simon Glassd2a98eb2021-12-01 09:02:53 -0700421 int i;
422
423 /* We need the DSDT to be done */
424 if (!ctx->dsdt)
425 return log_msg_ret("dsdt", -EAGAIN);
426
Simon Glass6fe570a2020-09-22 12:44:53 -0600427 /* Pack GNVS into the ACPI table area */
Simon Glass83c3cb52021-12-01 09:02:52 -0700428 for (i = 0; i < ctx->dsdt->length; i++) {
429 u32 *gnvs = (u32 *)((u32)ctx->dsdt + i);
Simon Glass0e113842020-04-26 09:19:47 -0600430
Simon Glass6fe570a2020-09-22 12:44:53 -0600431 if (*gnvs == ACPI_GNVS_ADDR) {
Simon Glass919f8352023-12-31 08:25:54 -0700432 *gnvs = nomap_to_sysmem(ctx->current);
Simon Glassd2a98eb2021-12-01 09:02:53 -0700433 log_debug("Fix up global NVS in DSDT to %#08x\n",
434 *gnvs);
Simon Glass6fe570a2020-09-22 12:44:53 -0600435 break;
436 }
Bin Mengd9050c62016-06-17 02:13:16 -0700437 }
Simon Glass6fe570a2020-09-22 12:44:53 -0600438
439 /*
Simon Glassd2a98eb2021-12-01 09:02:53 -0700440 * Recalculate the length and update the DSDT checksum since we
441 * patched the GNVS address. Set the checksum to zero since it
442 * is part of the region being checksummed.
Simon Glass6fe570a2020-09-22 12:44:53 -0600443 */
Simon Glassd2a98eb2021-12-01 09:02:53 -0700444 ctx->dsdt->checksum = 0;
445 ctx->dsdt->checksum = table_compute_checksum((void *)ctx->dsdt,
446 ctx->dsdt->length);
Bin Mengd9050c62016-06-17 02:13:16 -0700447 }
448
Simon Glassd2a98eb2021-12-01 09:02:53 -0700449 /* Fill in platform-specific global NVS variables */
Simon Glass9ed41e72020-07-07 21:32:05 -0600450 addr = acpi_create_gnvs(ctx->current);
451 if (IS_ERR_VALUE(addr))
Simon Glassd2a98eb2021-12-01 09:02:53 -0700452 return log_msg_ret("gnvs", (int)addr);
Simon Glass9ed41e72020-07-07 21:32:05 -0600453
Simon Glass0e113842020-04-26 09:19:47 -0600454 acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
Bin Mengd9050c62016-06-17 02:13:16 -0700455
Simon Glassd2a98eb2021-12-01 09:02:53 -0700456 return 0;
457}
458ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
459
Simon Glass4ffe8b02020-09-22 12:45:09 -0600460/**
461 * acpi_write_hpet() - Write out a HPET table
462 *
463 * Write out the table for High-Precision Event Timers
464 *
465 * @hpet: Place to put HPET table
466 */
467static int acpi_create_hpet(struct acpi_hpet *hpet)
468{
469 struct acpi_table_header *header = &hpet->header;
470 struct acpi_gen_regaddr *addr = &hpet->addr;
471
472 /*
473 * See IA-PC HPET (High Precision Event Timers) Specification v1.0a
474 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf
475 */
476 memset((void *)hpet, '\0', sizeof(struct acpi_hpet));
477
478 /* Fill out header fields. */
479 acpi_fill_header(header, "HPET");
480
Heinrich Schuchardt10de8a82024-01-21 12:52:48 +0100481 header->creator_revision = ASL_REVISION;
Simon Glass4ffe8b02020-09-22 12:45:09 -0600482 header->length = sizeof(struct acpi_hpet);
483 header->revision = acpi_get_table_revision(ACPITAB_HPET);
484
485 /* Fill out HPET address */
486 addr->space_id = 0; /* Memory */
487 addr->bit_width = 64;
488 addr->bit_offset = 0;
489 addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
490 addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
491
492 hpet->id = *(u32 *)CONFIG_HPET_ADDRESS;
493 hpet->number = 0;
494 hpet->min_tick = 0; /* HPET_MIN_TICKS */
495
496 header->checksum = table_compute_checksum(hpet,
497 sizeof(struct acpi_hpet));
498
499 return 0;
500}
501
502int acpi_write_hpet(struct acpi_ctx *ctx)
503{
504 struct acpi_hpet *hpet;
505 int ret;
506
507 log_debug("ACPI: * HPET\n");
508
509 hpet = ctx->current;
510 acpi_inc_align(ctx, sizeof(struct acpi_hpet));
511 acpi_create_hpet(hpet);
512 ret = acpi_add_table(ctx, hpet);
513 if (ret)
514 return log_msg_ret("add", ret);
515
516 return 0;
517}
Simon Glass95971892020-09-22 12:45:10 -0600518
519int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
520 uint access_size)
521{
522 struct acpi_dbg2_header *dbg2 = ctx->current;
523 char path[ACPI_PATH_MAX];
524 struct acpi_gen_regaddr address;
525 phys_addr_t addr;
526 int ret;
527
528 if (!device_active(dev)) {
529 log_info("Device not enabled\n");
530 return -EACCES;
531 }
532 /*
533 * PCI devices don't remember their resource allocation information in
534 * U-Boot at present. We assume that MMIO is used for the UART and that
535 * the address space is 32 bytes: ns16550 uses 8 registers of up to
536 * 32-bits each. This is only for debugging so it is not a big deal.
537 */
538 addr = dm_pci_read_bar32(dev, 0);
Simon Glass75081202020-11-04 09:57:41 -0700539 log_debug("UART addr %lx\n", (ulong)addr);
Simon Glass95971892020-09-22 12:45:10 -0600540
541 memset(&address, '\0', sizeof(address));
542 address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
543 address.addrl = (uint32_t)addr;
544 address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
545 address.access_size = access_size;
546
547 ret = acpi_device_path(dev, path, sizeof(path));
548 if (ret)
549 return log_msg_ret("path", ret);
550 acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
551 ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
552
553 acpi_inc_align(ctx, dbg2->header.length);
554 acpi_add_table(ctx, dbg2);
555
556 return 0;
557}
Simon Glass87cf8d22020-09-22 12:45:16 -0600558
559void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
560 void *dsdt)
561{
562 struct acpi_table_header *header = &fadt->header;
563
564 memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
565
566 acpi_fill_header(header, "FACP");
567 header->length = sizeof(struct acpi_fadt);
568 header->revision = 4;
569 memcpy(header->oem_id, OEM_ID, 6);
570 memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
Heinrich Schuchardt10de8a82024-01-21 12:52:48 +0100571 memcpy(header->creator_id, ASLC_ID, 4);
572 header->creator_revision = 1;
Simon Glass87cf8d22020-09-22 12:45:16 -0600573
Heinrich Schuchardtec958062023-12-16 09:11:57 +0100574 fadt->x_firmware_ctrl = map_to_sysmem(facs);
575 fadt->x_dsdt = map_to_sysmem(dsdt);
Simon Glass87cf8d22020-09-22 12:45:16 -0600576
577 fadt->preferred_pm_profile = ACPI_PM_MOBILE;
578
579 /* Use ACPI 3.0 revision */
580 fadt->header.revision = 4;
581}
582
583void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
584 u64 bar)
585{
586 struct dmar_entry *drhd = ctx->current;
587
588 memset(drhd, '\0', sizeof(*drhd));
589 drhd->type = DMAR_DRHD;
590 drhd->length = sizeof(*drhd); /* will be fixed up later */
591 drhd->flags = flags;
592 drhd->segment = segment;
593 drhd->bar = bar;
594 acpi_inc(ctx, drhd->length);
595}
596
597void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
598 u64 limit)
599{
600 struct dmar_rmrr_entry *rmrr = ctx->current;
601
602 memset(rmrr, '\0', sizeof(*rmrr));
603 rmrr->type = DMAR_RMRR;
604 rmrr->length = sizeof(*rmrr); /* will be fixed up later */
605 rmrr->segment = segment;
606 rmrr->bar = bar;
607 rmrr->limit = limit;
608 acpi_inc(ctx, rmrr->length);
609}
610
611void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base)
612{
613 struct dmar_entry *drhd = base;
614
615 drhd->length = ctx->current - base;
616}
617
618void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base)
619{
620 struct dmar_rmrr_entry *rmrr = base;
621
622 rmrr->length = ctx->current - base;
623}
624
625static int acpi_create_dmar_ds(struct acpi_ctx *ctx, enum dev_scope_type type,
626 uint enumeration_id, pci_dev_t bdf)
627{
628 /* we don't support longer paths yet */
629 const size_t dev_scope_length = sizeof(struct dev_scope) + 2;
630 struct dev_scope *ds = ctx->current;
631
632 memset(ds, '\0', dev_scope_length);
633 ds->type = type;
634 ds->length = dev_scope_length;
635 ds->enumeration = enumeration_id;
636 ds->start_bus = PCI_BUS(bdf);
637 ds->path[0].dev = PCI_DEV(bdf);
638 ds->path[0].fn = PCI_FUNC(bdf);
639
640 return ds->length;
641}
642
643int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf)
644{
645 return acpi_create_dmar_ds(ctx, SCOPE_PCI_SUB, 0, bdf);
646}
647
648int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf)
649{
650 return acpi_create_dmar_ds(ctx, SCOPE_PCI_ENDPOINT, 0, bdf);
651}
652
653int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
654 pci_dev_t bdf)
655{
656 return acpi_create_dmar_ds(ctx, SCOPE_IOAPIC, enumeration_id, bdf);
657}
658
659int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
660 pci_dev_t bdf)
661{
662 return acpi_create_dmar_ds(ctx, SCOPE_MSI_HPET, enumeration_id, bdf);
663}