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Miquel Raynalf3b43502018-05-15 11:57:08 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) 2018 Bootlin
4 * Author: Miquel Raynal <miquel.raynal@bootlin.com>
5 */
6
7#ifndef __TPM_V2_H
8#define __TPM_V2_H
9
10#include <tpm-common.h>
11
12#define TPM2_DIGEST_LEN 32
13
14/**
15 * TPM2 Structure Tags for command/response buffers.
16 *
17 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
18 * @TPM2_ST_SESSIONS: the command needs an authentication.
19 */
20enum tpm2_structures {
21 TPM2_ST_NO_SESSIONS = 0x8001,
22 TPM2_ST_SESSIONS = 0x8002,
23};
24
25/**
26 * TPM2 type of boolean.
27 */
28enum tpm2_yes_no {
29 TPMI_YES = 1,
30 TPMI_NO = 0,
31};
32
33/**
34 * TPM2 startup values.
35 *
36 * @TPM2_SU_CLEAR: reset the internal state.
37 * @TPM2_SU_STATE: restore saved state (if any).
38 */
39enum tpm2_startup_types {
40 TPM2_SU_CLEAR = 0x0000,
41 TPM2_SU_STATE = 0x0001,
42};
43
44/**
45 * TPM2 permanent handles.
46 *
47 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
48 * @TPM2_RS_PW: indicates a password.
49 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
50 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
51 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
52 */
53enum tpm2_handles {
54 TPM2_RH_OWNER = 0x40000001,
55 TPM2_RS_PW = 0x40000009,
56 TPM2_RH_LOCKOUT = 0x4000000A,
57 TPM2_RH_ENDORSEMENT = 0x4000000B,
58 TPM2_RH_PLATFORM = 0x4000000C,
59};
60
61/**
62 * TPM2 command codes used at the beginning of a buffer, gives the command.
63 *
64 * @TPM2_CC_STARTUP: TPM2_Startup().
65 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
66 * @TPM2_CC_CLEAR: TPM2_Clear().
67 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
68 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
69 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
70 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
71 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
72 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
Dhananjay Phadke7a2cf2e2020-06-04 16:43:59 -070073 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
Miquel Raynalf3b43502018-05-15 11:57:08 +020074 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
75 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
76 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
77 */
78enum tpm2_command_codes {
79 TPM2_CC_STARTUP = 0x0144,
80 TPM2_CC_SELF_TEST = 0x0143,
81 TPM2_CC_CLEAR = 0x0126,
82 TPM2_CC_CLEARCONTROL = 0x0127,
83 TPM2_CC_HIERCHANGEAUTH = 0x0129,
Miquel Raynal0b864f62018-05-15 11:57:20 +020084 TPM2_CC_PCR_SETAUTHPOL = 0x012C,
Miquel Raynalf3b43502018-05-15 11:57:08 +020085 TPM2_CC_DAM_RESET = 0x0139,
86 TPM2_CC_DAM_PARAMETERS = 0x013A,
Simon Glass5ff3f162018-10-01 11:55:17 -060087 TPM2_CC_NV_READ = 0x014E,
Miquel Raynalf3b43502018-05-15 11:57:08 +020088 TPM2_CC_GET_CAPABILITY = 0x017A,
Dhananjay Phadke7a2cf2e2020-06-04 16:43:59 -070089 TPM2_CC_GET_RANDOM = 0x017B,
Miquel Raynalf3b43502018-05-15 11:57:08 +020090 TPM2_CC_PCR_READ = 0x017E,
91 TPM2_CC_PCR_EXTEND = 0x0182,
Miquel Raynal0b864f62018-05-15 11:57:20 +020092 TPM2_CC_PCR_SETAUTHVAL = 0x0183,
Miquel Raynalf3b43502018-05-15 11:57:08 +020093};
94
95/**
96 * TPM2 return codes.
97 */
98enum tpm2_return_codes {
99 TPM2_RC_SUCCESS = 0x0000,
100 TPM2_RC_BAD_TAG = 0x001E,
101 TPM2_RC_FMT1 = 0x0080,
102 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
103 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
104 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
105 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
106 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
107 TPM2_RC_VER1 = 0x0100,
108 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
109 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
110 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
111 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
112 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
113 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
114 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
115 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
116 TPM2_RC_WARN = 0x0900,
117 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
118 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
119 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
120};
121
122/**
123 * TPM2 algorithms.
124 */
125enum tpm2_algorithms {
126 TPM2_ALG_XOR = 0x0A,
127 TPM2_ALG_SHA256 = 0x0B,
128 TPM2_ALG_SHA384 = 0x0C,
129 TPM2_ALG_SHA512 = 0x0D,
130 TPM2_ALG_NULL = 0x10,
131};
132
Simon Glassb4ebd1f2018-11-23 21:29:34 -0700133/* NV index attributes */
134enum tpm_index_attrs {
135 TPMA_NV_PPWRITE = 1UL << 0,
136 TPMA_NV_OWNERWRITE = 1UL << 1,
137 TPMA_NV_AUTHWRITE = 1UL << 2,
138 TPMA_NV_POLICYWRITE = 1UL << 3,
139 TPMA_NV_COUNTER = 1UL << 4,
140 TPMA_NV_BITS = 1UL << 5,
141 TPMA_NV_EXTEND = 1UL << 6,
142 TPMA_NV_POLICY_DELETE = 1UL << 10,
143 TPMA_NV_WRITELOCKED = 1UL << 11,
144 TPMA_NV_WRITEALL = 1UL << 12,
145 TPMA_NV_WRITEDEFINE = 1UL << 13,
146 TPMA_NV_WRITE_STCLEAR = 1UL << 14,
147 TPMA_NV_GLOBALLOCK = 1UL << 15,
148 TPMA_NV_PPREAD = 1UL << 16,
149 TPMA_NV_OWNERREAD = 1UL << 17,
150 TPMA_NV_AUTHREAD = 1UL << 18,
151 TPMA_NV_POLICYREAD = 1UL << 19,
152 TPMA_NV_NO_DA = 1UL << 25,
153 TPMA_NV_ORDERLY = 1UL << 26,
154 TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
155 TPMA_NV_READLOCKED = 1UL << 28,
156 TPMA_NV_WRITTEN = 1UL << 29,
157 TPMA_NV_PLATFORMCREATE = 1UL << 30,
158 TPMA_NV_READ_STCLEAR = 1UL << 31,
159
160 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
161 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
162 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
163 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
164};
165
Simon Glasse1ed0ec2020-02-06 09:55:03 -0700166enum {
167 TPM_ACCESS_VALID = 1 << 7,
168 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
169 TPM_ACCESS_REQUEST_PENDING = 1 << 2,
170 TPM_ACCESS_REQUEST_USE = 1 << 1,
171 TPM_ACCESS_ESTABLISHMENT = 1 << 0,
172};
173
174enum {
175 TPM_STS_FAMILY_SHIFT = 26,
176 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
177 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
178 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
179 TPM_STS_COMMAND_CANCEL = 1 << 24,
180 TPM_STS_BURST_COUNT_SHIFT = 8,
181 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
182 TPM_STS_VALID = 1 << 7,
183 TPM_STS_COMMAND_READY = 1 << 6,
184 TPM_STS_GO = 1 << 5,
185 TPM_STS_DATA_AVAIL = 1 << 4,
186 TPM_STS_DATA_EXPECT = 1 << 3,
187 TPM_STS_SELF_TEST_DONE = 1 << 2,
188 TPM_STS_RESPONSE_RETRY = 1 << 1,
189};
190
191enum {
192 TPM_CMD_COUNT_OFFSET = 2,
193 TPM_CMD_ORDINAL_OFFSET = 6,
194 TPM_MAX_BUF_SIZE = 1260,
195};
196
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200197/**
198 * Issue a TPM2_Startup command.
199 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700200 * @dev TPM device
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200201 * @mode TPM startup mode
202 *
203 * @return code of the operation
204 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700205u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200206
Miquel Raynal39c76082018-05-15 11:57:13 +0200207/**
208 * Issue a TPM2_SelfTest command.
209 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700210 * @dev TPM device
Miquel Raynal39c76082018-05-15 11:57:13 +0200211 * @full_test Asking to perform all tests or only the untested ones
212 *
213 * @return code of the operation
214 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700215u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
Miquel Raynal39c76082018-05-15 11:57:13 +0200216
Miquel Raynal8df6f8d2018-05-15 11:57:14 +0200217/**
218 * Issue a TPM2_Clear command.
219 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700220 * @dev TPM device
Miquel Raynal8df6f8d2018-05-15 11:57:14 +0200221 * @handle Handle
222 * @pw Password
223 * @pw_sz Length of the password
224 *
225 * @return code of the operation
226 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700227u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
228 const ssize_t pw_sz);
Miquel Raynal8df6f8d2018-05-15 11:57:14 +0200229
Miquel Raynal14d72352018-05-15 11:57:15 +0200230/**
231 * Issue a TPM2_PCR_Extend command.
232 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700233 * @dev TPM device
Miquel Raynal14d72352018-05-15 11:57:15 +0200234 * @index Index of the PCR
235 * @digest Value representing the event to be recorded
236 *
237 * @return code of the operation
238 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700239u32 tpm2_pcr_extend(struct udevice *dev, u32 index, const uint8_t *digest);
Miquel Raynal14d72352018-05-15 11:57:15 +0200240
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200241/**
242 * Issue a TPM2_PCR_Read command.
243 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700244 * @dev TPM device
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200245 * @idx Index of the PCR
246 * @idx_min_sz Minimum size in bytes of the pcrSelect array
247 * @data Output buffer for contents of the named PCR
248 * @updates Optional out parameter: number of updates for this PCR
249 *
250 * @return code of the operation
251 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700252u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
253 void *data, unsigned int *updates);
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200254
Miquel Raynal2e52c062018-05-15 11:57:17 +0200255/**
256 * Issue a TPM2_GetCapability command. This implementation is limited
257 * to query property index that is 4-byte wide.
258 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700259 * @dev TPM device
Miquel Raynal2e52c062018-05-15 11:57:17 +0200260 * @capability Partition of capabilities
261 * @property Further definition of capability, limited to be 4 bytes wide
262 * @buf Output buffer for capability information
263 * @prop_count Size of output buffer
264 *
265 * @return code of the operation
266 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700267u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
268 void *buf, size_t prop_count);
Miquel Raynal2e52c062018-05-15 11:57:17 +0200269
Miquel Raynal228e9902018-05-15 11:57:18 +0200270/**
271 * Issue a TPM2_DictionaryAttackLockReset command.
272 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700273 * @dev TPM device
Miquel Raynal228e9902018-05-15 11:57:18 +0200274 * @pw Password
275 * @pw_sz Length of the password
276 *
277 * @return code of the operation
278 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700279u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
Miquel Raynal228e9902018-05-15 11:57:18 +0200280
281/**
282 * Issue a TPM2_DictionaryAttackParameters command.
283 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700284 * @dev TPM device
Miquel Raynal228e9902018-05-15 11:57:18 +0200285 * @pw Password
286 * @pw_sz Length of the password
287 * @max_tries Count of authorizations before lockout
288 * @recovery_time Time before decrementation of the failure count
289 * @lockout_recovery Time to wait after a lockout
290 *
291 * @return code of the operation
292 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700293u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
294 const ssize_t pw_sz, unsigned int max_tries,
295 unsigned int recovery_time,
Miquel Raynal228e9902018-05-15 11:57:18 +0200296 unsigned int lockout_recovery);
297
Miquel Raynal05d7be32018-05-15 11:57:19 +0200298/**
299 * Issue a TPM2_HierarchyChangeAuth command.
300 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700301 * @dev TPM device
Miquel Raynal05d7be32018-05-15 11:57:19 +0200302 * @handle Handle
303 * @newpw New password
304 * @newpw_sz Length of the new password
305 * @oldpw Old password
306 * @oldpw_sz Length of the old password
307 *
308 * @return code of the operation
309 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700310int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
311 const ssize_t newpw_sz, const char *oldpw,
312 const ssize_t oldpw_sz);
Miquel Raynal05d7be32018-05-15 11:57:19 +0200313
Miquel Raynal0b864f62018-05-15 11:57:20 +0200314/**
315 * Issue a TPM_PCR_SetAuthPolicy command.
316 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700317 * @dev TPM device
Miquel Raynal0b864f62018-05-15 11:57:20 +0200318 * @pw Platform password
319 * @pw_sz Length of the password
320 * @index Index of the PCR
321 * @digest New key to access the PCR
322 *
323 * @return code of the operation
324 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700325u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
326 const ssize_t pw_sz, u32 index, const char *key);
Miquel Raynal0b864f62018-05-15 11:57:20 +0200327
328/**
329 * Issue a TPM_PCR_SetAuthValue command.
330 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700331 * @dev TPM device
Miquel Raynal0b864f62018-05-15 11:57:20 +0200332 * @pw Platform password
333 * @pw_sz Length of the password
334 * @index Index of the PCR
335 * @digest New key to access the PCR
336 * @key_sz Length of the new key
337 *
338 * @return code of the operation
339 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700340u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
341 const ssize_t pw_sz, u32 index, const char *key,
342 const ssize_t key_sz);
Miquel Raynal0b864f62018-05-15 11:57:20 +0200343
Dhananjay Phadke7a2cf2e2020-06-04 16:43:59 -0700344/**
345 * Issue a TPM2_GetRandom command.
346 *
347 * @dev TPM device
348 * @param data output buffer for the random bytes
349 * @param count size of output buffer
350 *
351 * @return return code of the operation
352 */
353u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
354
Miquel Raynalf3b43502018-05-15 11:57:08 +0200355#endif /* __TPM_V2_H */