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git01.mediatek.com / filogic / uboot / 3f7d94991ece943fde590e06fde96c86d67c8ac9 / . / dts / upstream / Bindings / dma / snps,dw-axi-dmac.yaml
blob: 363cf8bd150da2fe23e54b84d955f4392fb118b0 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare AXI DMA Controller
8
9maintainers:
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
11
12description:
13 Synopsys DesignWare AXI DMA Controller DT Binding
14
15allOf:
16 - $ref: dma-controller.yaml#
17
18properties:
19 compatible:
20 enum:
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
24
25 reg:
26 minItems: 1
27 items:
28 - description: Address range of the DMAC registers
29 - description: Address range of the DMAC APB registers
30
31 reg-names:
32 items:
33 - const: axidma_ctrl_regs
34 - const: axidma_apb_regs
35
36 interrupts:
37 description:
38 If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
39 will be per-channel interrupts. Otherwise, this is a single combined IRQ
40 for all channels.
41 minItems: 1
42 maxItems: 8
43
44 clocks:
45 items:
46 - description: Bus Clock
47 - description: Module Clock
48
49 clock-names:
50 items:
51 - const: core-clk
52 - const: cfgr-clk
53
54 '#dma-cells':
55 const: 1
56
57 dma-channels:
58 minimum: 1
59 maximum: 8
60
61 resets:
62 minItems: 1
63 maxItems: 2
64
65 snps,dma-masters:
66 description: |
67 Number of AXI masters supported by the hardware.
68 $ref: /schemas/types.yaml#/definitions/uint32
69 enum: [1, 2]
70
71 snps,data-width:
72 description: |
73 AXI data width supported by hardware.
74 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
75 $ref: /schemas/types.yaml#/definitions/uint32
76 enum: [0, 1, 2, 3, 4, 5, 6]
77
78 snps,priority:
79 description: |
80 Channel priority specifier associated with the DMA channels.
81 $ref: /schemas/types.yaml#/definitions/uint32-array
82 minItems: 1
83 maxItems: 8
84
85 snps,block-size:
86 description: |
87 Channel block size specifier associated with the DMA channels.
88 $ref: /schemas/types.yaml#/definitions/uint32-array
89 minItems: 1
90 maxItems: 8
91
92 snps,axi-max-burst-len:
93 description: |
94 Restrict master AXI burst length by value specified in this property.
95 If this property is missing the maximum AXI burst length supported by
96 DMAC is used.
97 $ref: /schemas/types.yaml#/definitions/uint32
98 minimum: 1
99 maximum: 256
100
101required:
102 - compatible
103 - reg
104 - clocks
105 - clock-names
106 - interrupts
107 - '#dma-cells'
108 - dma-channels
109 - snps,dma-masters
110 - snps,data-width
111 - snps,priority
112 - snps,block-size
113
114if:
115 properties:
116 compatible:
117 contains:
118 enum:
119 - starfive,jh7110-axi-dma
120then:
121 properties:
122 resets:
123 minItems: 2
124 items:
125 - description: AXI reset line
126 - description: AHB reset line
127 - description: module reset
128else:
129 properties:
130 resets:
131 maxItems: 1
132
133additionalProperties: false
134
135examples:
136 - |
137 #include <dt-bindings/interrupt-controller/arm-gic.h>
138 #include <dt-bindings/interrupt-controller/irq.h>
139 /* example with snps,dw-axi-dmac */
140 dma-controller@80000 {
141 compatible = "snps,axi-dma-1.01a";
142 reg = <0x80000 0x400>;
143 clocks = <&core_clk>, <&cfgr_clk>;
144 clock-names = "core-clk", "cfgr-clk";
145 interrupt-parent = <&intc>;
146 interrupts = <27>;
147 #dma-cells = <1>;
148 dma-channels = <4>;
149 snps,dma-masters = <2>;
150 snps,data-width = <3>;
151 snps,block-size = <4096 4096 4096 4096>;
152 snps,priority = <0 1 2 3>;
153 snps,axi-max-burst-len = <16>;
154 };