| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * Milbeaut AHB DMA Controller |
| 2 | |
| 3 | Milbeaut AHB DMA controller has transfer capability below. |
| 4 | - device to memory transfer |
| 5 | - memory to device transfer |
| 6 | |
| 7 | Required property: |
| 8 | - compatible: Should be "socionext,milbeaut-m10v-hdmac" |
| 9 | - reg: Should contain DMA registers location and length. |
| 10 | - interrupts: Should contain all of the per-channel DMA interrupts. |
| 11 | Number of channels is configurable - 2, 4 or 8, so |
| 12 | the number of interrupts specified should be {2,4,8}. |
| 13 | - #dma-cells: Should be 1. Specify the ID of the slave. |
| 14 | - clocks: Phandle to the clock used by the HDMAC module. |
| 15 | |
| 16 | |
| 17 | Example: |
| 18 | |
| 19 | hdmac1: dma-controller@1e110000 { |
| 20 | compatible = "socionext,milbeaut-m10v-hdmac"; |
| 21 | reg = <0x1e110000 0x10000>; |
| 22 | interrupts = <0 132 4>, |
| 23 | <0 133 4>, |
| 24 | <0 134 4>, |
| 25 | <0 135 4>, |
| 26 | <0 136 4>, |
| 27 | <0 137 4>, |
| 28 | <0 138 4>, |
| 29 | <0 139 4>; |
| 30 | #dma-cells = <1>; |
| 31 | clocks = <&dummy_clk>; |
| 32 | }; |