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wdenkc4cbd342005-01-09 18:21:42 +00001/*
2 * Configuation settings for the Sentec Cobra Board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/* ---
26 * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
27 * Date: 2004-03-29
28 * Author: Florian Schlote
29 *
30 * For a description of configuration options please refer also to the
31 * general u-boot-1.x.x/README file
32 * ---
33 */
34
35/* ---
36 * board/config.h - configuration options, board specific
37 * ---
38 */
39
40#ifndef _CONFIG_COBRA5272_H
41#define _CONFIG_COBRA5272_H
42
43/* ---
44 * Define processor
45 * possible values for Sentec board: only Coldfire M5272 processor supported
46 * (please do not change)
47 * ---
48 */
49
50#define CONFIG_MCF52x2 /* define processor family */
51#define CONFIG_M5272 /* define processor type */
52
53/* ---
54 * Defines processor clock - important for correct timings concerning serial
55 * interface etc.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056 * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
wdenkc4cbd342005-01-09 18:21:42 +000057 * ---
58 */
59
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_HZ 1000
61#define CONFIG_SYS_CLK 66000000
62#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenkc4cbd342005-01-09 18:21:42 +000063
64/* ---
65 * Enable use of Ethernet
66 * ---
67 */
TsiChungLiewcfa2b482007-08-15 19:41:06 -050068#define CONFIG_MCFFEC
wdenkc4cbd342005-01-09 18:21:42 +000069
TsiChungLiewcfa2b482007-08-15 19:41:06 -050070/* Enable Dma Timer */
71#define CONFIG_MCFTMR
wdenkc4cbd342005-01-09 18:21:42 +000072
73/* ---
74 * Define baudrate for UART1 (console output, tftp, ...)
75 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenkc4cbd342005-01-09 18:21:42 +000077 * interface
78 * ---
79 */
80
TsiChungLiewcfa2b482007-08-15 19:41:06 -050081#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_UART_PORT (0)
wdenkc4cbd342005-01-09 18:21:42 +000083#define CONFIG_BAUDRATE 19200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
wdenkc4cbd342005-01-09 18:21:42 +000085
86/* ---
87 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
88 * timeout acc. to your needs
89 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
90 * for 10 sec
91 * ---
92 */
93
94#if 0
95#define CONFIG_WATCHDOG
96#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
97#endif
98
99/* ---
100 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
101 * bootloader residing in flash ('chainloading'); if you want to use
102 * chainloading or want to compile a u-boot binary that can be loaded into
103 * RAM via BDM set
Wolfgang Denka1be4762008-05-20 16:00:29 +0200104 * "#if 0" to "#if 1"
wdenkc4cbd342005-01-09 18:21:42 +0000105 * You will need a first stage bootloader then, e. g. colilo or a working BDM
106 * cable (Background Debug Mode)
107 *
108 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
109 *
110 * Please do not forget to modify the setting of TEXT_BASE
111 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
112 *
113 * ---
114 */
115
116#if 0
117#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
118#endif
119
120/* ---
121 * Configuration for environment
122 * Environment is embedded in u-boot in the second sector of the flash
123 * ---
124 */
125
126#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200127#define CONFIG_ENV_OFFSET 0x4000
128#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200129#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc4cbd342005-01-09 18:21:42 +0000130#else
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200131#define CONFIG_ENV_ADDR 0xffe04000
132#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200133#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc4cbd342005-01-09 18:21:42 +0000134#endif
135
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500136
137/*
Jon Loeligere54e77a2007-07-10 09:29:01 -0500138 * BOOTP options
139 */
140#define CONFIG_BOOTP_BOOTFILESIZE
141#define CONFIG_BOOTP_BOOTPATH
142#define CONFIG_BOOTP_GATEWAY
143#define CONFIG_BOOTP_HOSTNAME
144
145
146/*
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500147 * Command line configuration.
wdenkc4cbd342005-01-09 18:21:42 +0000148 */
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500149#include <config_cmd_default.h>
wdenkc4cbd342005-01-09 18:21:42 +0000150
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500151#define CONFIG_CMD_PING
wdenkc4cbd342005-01-09 18:21:42 +0000152
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500153#undef CONFIG_CMD_LOADS
154#undef CONFIG_CMD_LOADB
155#undef CONFIG_CMD_MII
156
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500157#ifdef CONFIG_MCFFEC
158# define CONFIG_NET_MULTI 1
159# define CONFIG_MII 1
TsiChung Liewb3162452008-03-30 01:22:13 -0500160# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161# define CONFIG_SYS_DISCOVER_PHY
162# define CONFIG_SYS_RX_ETH_BUFFER 8
163# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500164
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165# define CONFIG_SYS_FEC0_PINMUX 0
166# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denka1be4762008-05-20 16:00:29 +0200167# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
169# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500170# define FECDUPLEX FULL
171# define FECSPEED _100BASET
172# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
174# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500175# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500177#endif
wdenkc4cbd342005-01-09 18:21:42 +0000178
179/*
180 *-----------------------------------------------------------------------------
181 * Define user parameters that have to be customized most likely
182 *-----------------------------------------------------------------------------
183 */
184
185/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
186
187#define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in
188seconds u-boot will wait before starting defined (auto-)boot command, setting
189to -1 disables delay, setting to 0 will too prevent access to u-boot command
190interface: u-boot then has to reflashed */
191
192
193/* The following settings will be contained in the environment block ; if you
194want to use a neutral environment all those settings can be manually set in
195u-boot: 'set' command */
196
197#if 0
198
199#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
200enter a valid image address in flash */
201
202#define CONFIG_BOOTARGS " " /* default bootargs that are
203considered during boot */
204
205/* User network settings */
206
207#define CONFIG_ETHADDR 00:00:00:00:00:09 /* default ethernet MAC addr. */
208#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
209#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
210
211#endif
212
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#define CONFIG_SYS_PROMPT "COBRA > " /* Layout of u-boot prompt*/
wdenkc4cbd342005-01-09 18:21:42 +0000214
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
wdenkc4cbd342005-01-09 18:21:42 +0000216from which user programs will be started */
217
218/*---*/
219
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkc4cbd342005-01-09 18:21:42 +0000221
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500222#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc4cbd342005-01-09 18:21:42 +0000224#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc4cbd342005-01-09 18:21:42 +0000226#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
228#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
229#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc4cbd342005-01-09 18:21:42 +0000230
231/*
232 *-----------------------------------------------------------------------------
233 * End of user parameters to be customized
234 *-----------------------------------------------------------------------------
235 */
236
237/* ---
238 * Defines memory range for test
239 * ---
240 */
241
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#define CONFIG_SYS_MEMTEST_START 0x400
243#define CONFIG_SYS_MEMTEST_END 0x380000
wdenkc4cbd342005-01-09 18:21:42 +0000244
245/* ---
246 * Low Level Configuration Settings
247 * (address mappings, register initial values, etc.)
248 * You should know what you are doing if you make changes here.
249 * ---
250 */
251
252/* ---
253 * Base register address
254 * ---
255 */
256
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenkc4cbd342005-01-09 18:21:42 +0000258
259/* ---
260 * System Conf. Reg. & System Protection Reg.
261 * ---
262 */
263
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_SCR 0x0003
265#define CONFIG_SYS_SPR 0xffff
wdenkc4cbd342005-01-09 18:21:42 +0000266
267/* ---
268 * Ethernet settings
269 * ---
270 */
271
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_DISCOVER_PHY
273#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenkc4cbd342005-01-09 18:21:42 +0000274
275/*-----------------------------------------------------------------------
276 * Definitions for initial stack pointer and data area (in internal SRAM)
277 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
279#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
280#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
281#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
282#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc4cbd342005-01-09 18:21:42 +0000283
284/*-----------------------------------------------------------------------
285 * Start addresses for the final memory configuration
286 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200287 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc4cbd342005-01-09 18:21:42 +0000288 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200289#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkc4cbd342005-01-09 18:21:42 +0000290
291/*
292 *-------------------------------------------------------------------------
293 * RAM SIZE (is defined above)
294 *-----------------------------------------------------------------------
295 */
296
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenkc4cbd342005-01-09 18:21:42 +0000298
299/*
300 *-----------------------------------------------------------------------
301 */
302
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkc4cbd342005-01-09 18:21:42 +0000304
305#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200306#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkc4cbd342005-01-09 18:21:42 +0000307#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200308#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkc4cbd342005-01-09 18:21:42 +0000309#endif
310
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200311#define CONFIG_SYS_MONITOR_LEN 0x20000
312#define CONFIG_SYS_MALLOC_LEN (256 << 10)
313#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkc4cbd342005-01-09 18:21:42 +0000314
315/*
316 * For booting Linux, the board info and command line data
317 * have to be in the first 8 MB of memory, since this is
318 * the maximum mapped by the Linux kernel during initialization ??
319 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200320#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc4cbd342005-01-09 18:21:42 +0000321
322/*-----------------------------------------------------------------------
323 * FLASH organization
324 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
326#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
327#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenkc4cbd342005-01-09 18:21:42 +0000328
329/*-----------------------------------------------------------------------
330 * Cache Configuration
331 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200332#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkc4cbd342005-01-09 18:21:42 +0000333
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600334#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
335 CONFIG_SYS_INIT_RAM_END - 8)
336#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
337 CONFIG_SYS_INIT_RAM_END - 4)
338#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
339#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
340 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
341 CF_ACR_EN | CF_ACR_SM_ALL)
342#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
343 CF_CACR_DISD | CF_CACR_INVI | \
344 CF_CACR_CEIB | CF_CACR_DCM | \
345 CF_CACR_EUSP)
346
wdenkc4cbd342005-01-09 18:21:42 +0000347/*-----------------------------------------------------------------------
348 * Memory bank definitions
349 *
350 * Please refer also to Motorola Coldfire user manual - Chapter XXX
351 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
352 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
354#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
wdenkc4cbd342005-01-09 18:21:42 +0000355
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200356#define CONFIG_SYS_BR1_PRELIM 0
357#define CONFIG_SYS_OR1_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000358
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200359#define CONFIG_SYS_BR2_PRELIM 0
360#define CONFIG_SYS_OR2_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000361
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200362#define CONFIG_SYS_BR3_PRELIM 0
363#define CONFIG_SYS_OR3_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000364
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200365#define CONFIG_SYS_BR4_PRELIM 0
366#define CONFIG_SYS_OR4_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000367
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_SYS_BR5_PRELIM 0
369#define CONFIG_SYS_OR5_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000370
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200371#define CONFIG_SYS_BR6_PRELIM 0
372#define CONFIG_SYS_OR6_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000373
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200374#define CONFIG_SYS_BR7_PRELIM 0x00000701
375#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
wdenkc4cbd342005-01-09 18:21:42 +0000376
377/*-----------------------------------------------------------------------
378 * LED config
379 */
380#define LED_STAT_0 0xffff /*all LEDs off*/
381#define LED_STAT_1 0xfffe
382#define LED_STAT_2 0xfffd
383#define LED_STAT_3 0xfffb
384#define LED_STAT_4 0xfff7
385#define LED_STAT_5 0xffef
386#define LED_STAT_6 0xffdf
387#define LED_STAT_7 0xff00 /*all LEDs on*/
388
389/*-----------------------------------------------------------------------
390 * Port configuration (GPIO)
391 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200392#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenkc4cbd342005-01-09 18:21:42 +0000393GPIO*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200394#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenkc4cbd342005-01-09 18:21:42 +0000395(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200396#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
397#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenkc4cbd342005-01-09 18:21:42 +0000398configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200399#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
400#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
401#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenkc4cbd342005-01-09 18:21:42 +0000402
403#endif /* _CONFIG_COBRA5272_H */