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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chunhe Lan66cba6b2015-03-20 17:08:54 +08002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 *
5 * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
Chunhe Lan66cba6b2015-03-20 17:08:54 +08006 */
7
8#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07009#include <clock_legacy.h>
Simon Glassa73bda42015-11-08 23:47:45 -070010#include <console.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060011#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -070012#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Chunhe Lan66cba6b2015-03-20 17:08:54 +080014#include <asm/spl.h>
15#include <malloc.h>
16#include <ns16550.h>
17#include <nand.h>
18#include <mmc.h>
19#include <fsl_esdhc.h>
20#include <i2c.h>
21
22#include "t4rdb.h"
23
24#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
25
26DECLARE_GLOBAL_DATA_PTR;
27
28phys_size_t get_effective_memsize(void)
29{
30 return CONFIG_SYS_L3_SIZE;
31}
32
33unsigned long get_board_sys_clk(void)
34{
35 return CONFIG_SYS_CLK_FREQ;
36}
37
38unsigned long get_board_ddr_clk(void)
39{
40 return CONFIG_DDR_CLK_FREQ;
41}
42
43void board_init_f(ulong bootflag)
44{
45 u32 plat_ratio, sys_clk, ccb_clk;
46 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
47
48 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
49 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
50
51 /* Update GD pointer */
52 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
53
54 /* compiler optimization barrier needed for GCC >= 3.4 */
55 __asm__ __volatile__("" : : : "memory");
56
57 console_init_f();
58
59 /* initialize selected port with appropriate baud rate */
60 sys_clk = get_board_sys_clk();
61 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
62 ccb_clk = sys_clk * plat_ratio / 2;
63
Simon Glass2b923982020-12-22 19:30:19 -070064 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
Chunhe Lan66cba6b2015-03-20 17:08:54 +080065 ccb_clk / 16 / CONFIG_BAUDRATE);
66
67 puts("\nSD boot...\n");
68
69 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
70}
71
72void board_init_r(gd_t *gd, ulong dest_addr)
73{
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090074 struct bd_info *bd;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080075
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090076 bd = (struct bd_info *)(gd + sizeof(gd_t));
77 memset(bd, 0, sizeof(struct bd_info));
Chunhe Lan66cba6b2015-03-20 17:08:54 +080078 gd->bd = bd;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080079
Simon Glass302445a2017-01-23 13:31:22 -070080 arch_cpu_init();
Chunhe Lan66cba6b2015-03-20 17:08:54 +080081 get_clocks();
82 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
83 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040084 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080085
86 mmc_initialize(bd);
87 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050088 (uchar *)SPL_ENV_ADDR);
Chunhe Lan66cba6b2015-03-20 17:08:54 +080089
Tom Rini5cd7ece2019-11-18 20:02:10 -050090 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -060091 gd->env_valid = ENV_VALID;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080092
93 i2c_init_all();
94
Simon Glassd35f3382017-04-06 12:47:05 -060095 dram_init();
Chunhe Lan66cba6b2015-03-20 17:08:54 +080096
97 mmc_boot();
98}