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git01.mediatek.com / filogic / uboot / 3f3b40ae1469f1a9fed9f3b9d6223ab155990186 / . / doc / README.dk1c20_std32
blob: 2be12998d312a4d6ebf7e312325ebf83b639c3e2 [file] [log] [blame]
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]1
2TODO: specify IDE i/f
3 specify ASMI i/f
4 specify OCI
5
6
7===============================================================================
8 C P U , M E M O R Y , I N / O U T C O M P O N E N T S
9===============================================================================
10see also [1]-[6]
11
12CPU: "standard_32"
13 32 bit NIOS for 50 MHz
14 256 Byte for register file (15 levels)
15 4 KByte instruction cache (2 bytes in each cache line)
16 4 KByte data cache (4 bytes in each cache line)
17 2 KByte On Chip ROM with GERMS boot monitor
18 no On Chip RAM
19 MSTEP multiplier
20 no Debug Core
21 On Chip Instrumentation (OCI) enabled
22
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]23 U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000
24 CONFIG_SYS_NIOS_CPU_ICACHE = 4096
25 CONFIG_SYS_NIOS_CPU_DCACHE = 4096
26 CONFIG_SYS_NIOS_CPU_REG_NUMS = 256
27 CONFIG_SYS_NIOS_CPU_MUL = 0
28 CONFIG_SYS_NIOS_CPU_MSTEP = 1
29 CONFIG_SYS_NIOS_CPU_DBG_CORE = 0
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]30
31OCI: (TODO)
32
33IRQ: Nr. | used by
34 ------+--------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]35 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
36 25 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 25
37 30 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 30
38 35 | PIO5 | CONFIG_SYS_NIOS_CPU_PIO5_IRQ = 35
39 40 | PIO0 | CONFIG_SYS_NIOS_CPU_PIO0_IRQ = 40
40 45 | ASMI | CONFIG_SYS_NIOS_CPU_ASMI0_IRQ = 45
41 50 | TIMER1 | CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]42
43MEMORY: 8 MByte Flash
44 1 MByte SRAM
45 16 MByte SDRAM
46
47ASMI: (TODO) <-- ASMI part is 4M bits
48
49Timer: TIMER0: high priority programmable timer (IRQ16)
50 TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
51
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]52 U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 1
53 CONFIG_SYS_NIOS_CPU_USER_TIMER = 0
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]54
55PIO: Nr. | description
56 ------+--------------------------------------------------------
57 PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
58 PIO1 | LCD: 11 in/outputs for ASCII LCD
59 PIO2 | LED: 8 outputs for user LEDs
60 PIO3 | SEVENSEG: 16 outputs for user seven segment display
61 PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
62 PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
63 PIO6 | CFPOWER: 1 output to controll CF power supply
64 PIO7 | CFATASEL: 1 output to controll CF ATA card select
65
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]66 U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 0
67 CONFIG_SYS_NIOS_CPU_LCD_PIO = 1
68 CONFIG_SYS_NIOS_CPU_LED_PIO = 2
69 CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 3
70 CONFIG_SYS_NIOS_CPU_RECONF_PIO = 4
71 CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = 5
72 CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 6
73 CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = 7
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]74
75UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
76 without handshake RTS/CTS (IRQ25)
77
78LAN: SMsC LAN91C111 with:
79 - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
80 - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
81
82IDE: (TODO)
83
84
85===============================================================================
86 M E M O R Y M A P
87===============================================================================
88
89- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
90
91 0x02000000 ---32-----------16|15------------0-
92 | : | \
93 | : | |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]94 SDRAM | : | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]95 | : | | = 0x01000000
96 | : | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]97 0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]98 | |
99 : gap :
100 : :
101
102- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
103
104 : :
105 : gap :
106 | |
107 0x________ ---32-----------16|15------------0-
108 | | | \
109 : (real size : : |
110 ASMI i/f : and content : : > 0x________
111 [5] : unknown) : : |
112 | | | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]113 0x00920b00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ASMI0
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]114 | |
115 : gap :
116 | |
117 0x00920a80 ---32-----------16|15------------0-
118 | | | \
119 : (real size : : |
120 IDE i/f : and content : : > 0x00000080
121 [6] : unknown) : : |
122 | | | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]123 0x00920a00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]124 | (unused) | \
125 + 0x1c |- - - - - - - - - - - - - - - -| |
126 | (unused) | |
127 + 0x18 |- - - - - - - - - - - - - - - -| |
128 | (unused) | |
129 + 0x14 |- - - - - - - - - - - - - - - -| |
130 TIMER1 | (unused) | |
131 [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
132 | (unused) | |
133 + 0x0c |- - - - - - - - - - - - - - - -| |
134 | (unused) | |
135 + 0x08 |- - - - - - - - - - - - - - - -| |
136 | control (1 bit) (rw) | |
137 + 0x04 |- - - - - - - - - - - - - - - -| |
138 | status (2 bit) (rw) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]139 0x009209e0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER1
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]140 | (unused) | \
141 + 0x0c |- - - - - - - - - - - - - - - -| |
142 PIO7 | (unused) | |
143 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
144 | (unused) | |
145 + 0x04 |- - - - - - - - - - - - - - - -| |
146 | data (1 bit) (wo) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]147 0x009209d0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO7
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]148 | (unused) | \
149 + 0x0c |- - - - - - - - - - - - - - - -| |
150 PIO6 | (unused) | |
151 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
152 | (unused) | |
153 + 0x04 |- - - - - - - - - - - - - - - -| |
154 | data (1 bit) (wo) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]155 0x009209c0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO6
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]156 | edgecapture (1 bit) (rw) | \
157 + 0x0c |- - - - - - - - - - - - - - - -| |
158 PIO5 | interruptmask (1 bit) (rw) | |
159 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
160 | (unused) | |
161 + 0x04 |- - - - - - - - - - - - - - - -| |
162 | data (1 bit) (ro) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]163 0x009209b0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO5
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]164 | (unused) | \
165 + 0x0c |- - - - - - - - - - - - - - - -| |
166 PIO4 | (unused) | |
167 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
168 | direction (1 bit) (rw) | |
169 + 0x04 |- - - - - - - - - - - - - - - -| |
170 | data (1 bit) (rw) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]171 0x009209a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO4
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]172 | (unused) | \
173 + 0x0c |- - - - - - - - - - - - - - - -| |
174 PIO3 | (unused) | |
175 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
176 | (unused) | |
177 + 0x04 |- - - - - - - - - - - - - - - -| |
178 | data (16 bit) (wo) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]179 0x00920990 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO3
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]180 | (unused) | \
181 + 0x0c |- - - - - - - - - - - - - - - -| |
182 PIO2 | (unused) | |
183 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
184 | (unused) | |
185 + 0x04 |- - - - - - - - - - - - - - - -| |
186 | data (8 bit) (wo) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]187 0x00920980 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO2
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]188 | (unused) | \
189 + 0x0c |- - - - - - - - - - - - - - - -| |
190 PIO1 | (unused) | |
191 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
192 | direction (11 bit) (rw) | |
193 + 0x04 |- - - - - - - - - - - - - - - -| |
194 | data (11 bit) (rw) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]195 0x00920970 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]196 | edgecapture (4 bit) (rw) | \
197 + 0x0c |- - - - - - - - - - - - - - - -| |
198 PIO0 | interruptmask (4 bit) (rw) | |
199 [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
200 | (unused) | |
201 + 0x04 |- - - - - - - - - - - - - - - -| |
202 | data (4 bit) (ro) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]203 0x00920960 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]204 | (unused) | \
205 + 0x1c |- - - - - - - - - - - - - - - -| |
206 | (unused) | |
207 + 0x18 |- - - - - - - - - - - - - - - -| |
208 | snaph (16 bit) (rw) | |
209 + 0x14 |- - - - - - - - - - - - - - - -| |
210 TIMER0 | snapl (16 bit) (rw) | |
211 [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
212 | periodh (16 bit) (rw) | |
213 + 0x0c |- - - - - - - - - - - - - - - -| |
214 | periodl (16 bit) (rw) | |
215 + 0x08 |- - - - - - - - - - - - - - - -| |
216 | control (4 bit) (rw) | |
217 + 0x04 |- - - - - - - - - - - - - - - -| |
218 | status (2 bit) (rw) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]219 0x00920940 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]220 | | \
221 : gap : > (space for UART1)
222 | | /
223 0x00920920 ---32-----------16|15------------0-
224 | (unused) | \
225 + 0x1c |- - - - - - - - - - - - - - - -| |
226 | (unused) | |
227 + 0x18 |- - - - - - - - - - - - - - - -| |
228 | (unused) | |
229 + 0x14 |- - - - - - - - - - - - - - - -| |
230 UART0 | (unused) | > 0x00000020
231 [2] + 0x10 |- - - - - - - - - - - - - - - -| |
232 | control (10 bit) (rw) | |
233 + 0x0c |- - - - - - - - - - - - - - - -| |
234 | status (10 bit) (rw) | |
235 + 0x08 |- - - - - - - - - - - - - - - -| |
236 | txdata (8 bit) (wo) | |
237 + 0x04 |- - - - - - - - - - - - - - - -| |
238 | rxdata (8 bit) (ro) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]239 0x00920900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]240
241- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
242
243 0x00920900 -----------------------------------
244 | | \
245 : (real size : |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]246 OCI Debug : and content : > CONFIG_SYS_NIOS_CPU_OCI_SIZE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]247 : unknown) : | = 0x00000100
248 | | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]249 0x00920800 ----------------------------------- CONFIG_SYS_NIOS_CPU_OCI_BASE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]250
251- - - - - - - - - - - on chip memory - - - - - - - - - - -
252
253 0x00920800 ---32-----------16|15------------0-
254 | : | \
255 | : | |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]256 GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]257 | : | | = 0x00000800
258 | : | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]259 0x00920000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
260 0x00920000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]261
262- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
263
264 0x00920000 ---32-----------16|15------------0-
265 | gap | \
266 0x00910310 --+-------------------------------| |
267 | | |
268 | register bank (size = 0x10) | |
269 | +--------.---.---.--- | |
270 | | bank 0 \ 1 \ 2 \ 3 \ | |
271 | |---------------------------+ | |
272 LAN91C111 | | BANK | RESERVED | | |
273 | |- - - - - - -|- - - - - - -| | > na_lan91c111_size
274 | | RPCR | MIR | | | = 0x00010000
275 | |- - - - - - -|- - - - - - -| | |
276 | | COUNTER | RCR | | |
277 | |- - - - - - -|- - - - - - -| | |
278 | | EPH STATUS | TCR | | |
279 | +---------------------------+ | |
280 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
281 | gap | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]282 0x00910000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]283 | |
284 : gap :
285 : :
286
287- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
288
289 : :
290 : gap :
291 | |
292 0x00900000 ---32-----------16|15------------0-
293 0x00900000 --+32-----------16|15------------0+
294 | : | \ \
295 | : | | |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]296 | : | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]297 | : | | | = 0x00000100
298 | : | | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]299 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
300 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]301 | : | | \
302 | : | | |
303 | : | | > stack area
304 | : | | |
305 | : | | V
306 | : | |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]307 SRAM | : | > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]308 | : | | = 0x00100000
309 | : | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]310 0x00800000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]311 0x00800000 ---8-------------4|3-------------0-
312 | sector 127 | \
313 + 0x7f0000 |- - - - - - - - - - - - - - - -| |
314 | : | |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]315 Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]316 | sector 1 : | | = 0x00800000
317 + 0x010000 |- - - - - - - - - - - - - - - -| |
318 | sector 0 (size = 0x10000) | /
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]319 0x00000000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]320
321
322===============================================================================
323 F L A S H M E M O R Y A L L O C A T I O N
324===============================================================================
325
326 0x00800000 ---8-------------4|3-------------0-
327 | : | \
328 SAFE | : | > 1 MByte
329 FPGA conf. | : | / (NOT usable by software)
330 0x00700000 --+- - - - - - - -:- - - - - - - -+-
331 | : | \
332 USER | : | > 1 MByte
333 FPGA conf. | : | / (NOT usable by software)
334 0x00600000 --+- - - - - - - -:- - - - - - - -+-
335 | : | \
336 | : | |
337 WEB pages | : | > 2 MByte
338 | : | | (provisory usable)
339 | : | /
340 0x00400000 --+- - - - - - - -:- - - - - - - -+-
341 | : | \
342 | : | |
343 | : | |
344 | : | > 4 MByte free for use
345 | : | |
346 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
347 | : | /
wdenkc0bc2e12004-02-09 23:12:24 +0000[diff] [blame]348 0x00000000 |- - - - - - - -:- - - - - - - -+- - u-boot environment
wdenk3be717f2004-01-03 19:43:48 +0000[diff] [blame]349 0x00000000 ---8-------------4|3-------------0-
350
351
352===============================================================================
353 R E F E R E N C E S
354===============================================================================
355[1] http://www.altera.com/literature/manual/mnl_nios_board_cyclone_1c20.pdf
356[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
357[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
358[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
359[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf
360 http://www.altera.com/literature/wp/wp_epcs_cyc.pdf
361[6] http://www.opencores.org/projects/ata/
362 http://www.t13.org/index.html
363
364
365===============================================================================
366Stephan Linz <linz@li-pro.net>