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git01.mediatek.com / filogic / uboot / 3f3a309d05025f9366df516f5cbd5cf94327675e / . / board / xes / xpedite1000 / u-boot.lds.debug
blob: 04089ae7e51fdae41667b7248b531cccd32b2c4c [file] [log] [blame]
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1/*
2 * (C) Copyright 2002-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]6 */
7
8OUTPUT_ARCH(powerpc)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]9/* Do we need any of these for elf?
10 __DYNAMIC = 0; */
11SECTIONS
12{
13 /* Read-only sections, merged into text segment: */
14 . = + SIZEOF_HEADERS;
15 .interp : { *(.interp) }
16 .hash : { *(.hash) }
17 .dynsym : { *(.dynsym) }
18 .dynstr : { *(.dynstr) }
19 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]20 .rela.text : { *(.rela.text) }
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]21 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]22 .rela.data : { *(.rela.data) }
23 .rel.rodata : { *(.rel.rodata) }
24 .rela.rodata : { *(.rela.rodata) }
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]25 .rel.got : { *(.rel.got) }
26 .rela.got : { *(.rela.got) }
27 .rel.ctors : { *(.rel.ctors) }
28 .rela.ctors : { *(.rela.ctors) }
29 .rel.dtors : { *(.rel.dtors) }
30 .rela.dtors : { *(.rela.dtors) }
31 .rel.bss : { *(.rel.bss) }
32 .rela.bss : { *(.rela.bss) }
33 .rel.plt : { *(.rel.plt) }
34 .rela.plt : { *(.rela.plt) }
35 .init : { *(.init) }
36 .plt : { *(.plt) }
37 .text :
38 {
39 /* WARNING - the following is hand-optimized to fit within */
40 /* the sector layout of our flash chips! XXX FIXME XXX */
41
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]42 arch/powerpc/cpu/ppc4xx/start.o (.text)
Peter Tyser20934772009-07-17 19:01:16 -0500[diff] [blame]43 board/xes/xpedite1000/init.o (.text)
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]44 arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
45 arch/powerpc/cpu/ppc4xx/traps.o (.text)
46 arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
47 arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
48 arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
49 arch/powerpc/cpu/ppc4xx/speed.o (.text)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]50 common/dlmalloc.o (.text)
Peter Tyser685b7f52010-04-12 22:28:05 -0500[diff] [blame]51 lib/crc32.o (.text)
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]52 arch/powerpc/lib/extable.o (.text)
Peter Tyser685b7f52010-04-12 22:28:05 -0500[diff] [blame]53 lib/zlib.o (.text)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]54
Jean-Christophe PLAGNIOL-VILLARD4436c1e2008-09-10 22:48:01 +0200[diff] [blame]55/* common/env_embedded.o(.text) */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]56
57 *(.text)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]58 *(.got1)
59 }
60 _etext = .;
61 PROVIDE (etext = .);
62 .rodata :
63 {
Wolfgang Denkaaa7c002005-12-12 16:06:05 +0100[diff] [blame]64 *(.eh_frame)
Trent Piepho4438e5e2009-02-18 15:22:05 -0800[diff] [blame]65 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]66 }
67 .fini : { *(.fini) } =0
68 .ctors : { *(.ctors) }
69 .dtors : { *(.dtors) }
70
71 /* Read-write section, merged into data segment: */
72 . = (. + 0x0FFF) & 0xFFFFF000;
73 _erotext = .;
74 PROVIDE (erotext = .);
75 .reloc :
76 {
77 *(.got)
78 _GOT2_TABLE_ = .;
79 *(.got2)
80 _FIXUP_TABLE_ = .;
81 *(.fixup)
82 }
83 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
84 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
85
86 .data :
87 {
88 *(.data)
89 *(.data1)
90 *(.sdata)
91 *(.sdata2)
92 *(.dynamic)
93 CONSTRUCTORS
94 }
95 _edata = .;
96 PROVIDE (edata = .);
97
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]98
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]99 . = ALIGN(4);
100 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]101 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]102 }
103
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]104
105 __start___ex_table = .;
106 __ex_table : { *(__ex_table) }
107 __stop___ex_table = .;
108
109 . = ALIGN(256);
110 __init_begin = .;
111 .text.init : { *(.text.init) }
112 .data.init : { *(.data.init) }
113 . = ALIGN(256);
114 __init_end = .;
115
116 __bss_start = .;
117 .bss :
118 {
119 *(.sbss) *(.scommon)
120 *(.dynbss)
121 *(.bss)
122 *(COMMON)
123 }
Albert ARIBAUD0198f9d2013-03-30 00:19:53 +0000[diff] [blame]124 __bss_end = . ;
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]125 PROVIDE (end = .);
126}