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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc6097192002-11-03 00:24:07 +000020#define CONFIG_PIP405 1 /* ...on a PIP405 board */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020021
22#define CONFIG_SYS_TEXT_BASE 0xFFF80000
23
David Müller (ELSOFT AG)789d3122014-09-30 12:32:20 +020024#define CONFIG_SYS_GENERIC_BOARD
25
wdenkc6097192002-11-03 00:24:07 +000026/***********************************************************
27 * Clock
28 ***********************************************************/
29#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
30
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050031
32/*
Jon Loeligerbeb9ff42007-07-10 09:22:23 -050033 * BOOTP options
34 */
35#define CONFIG_BOOTP_BOOTFILESIZE
36#define CONFIG_BOOTP_BOOTPATH
37#define CONFIG_BOOTP_GATEWAY
38#define CONFIG_BOOTP_HOSTNAME
39
40
41/*
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050042 * Command line configuration.
43 */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050044#define CONFIG_CMD_IDE
45#define CONFIG_CMD_DHCP
46#define CONFIG_CMD_PCI
47#define CONFIG_CMD_CACHE
48#define CONFIG_CMD_IRQ
49#define CONFIG_CMD_EEPROM
50#define CONFIG_CMD_I2C
51#define CONFIG_CMD_REGINFO
52#define CONFIG_CMD_FDC
53#define CONFIG_CMD_SCSI
54#define CONFIG_CMD_FAT
55#define CONFIG_CMD_DATE
56#define CONFIG_CMD_ELF
57#define CONFIG_CMD_USB
58#define CONFIG_CMD_MII
59#define CONFIG_CMD_SDRAM
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050060#define CONFIG_CMD_PING
61#define CONFIG_CMD_SAVES
62#define CONFIG_CMD_BSP
63
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_HUSH_PARSER
wdenkc6097192002-11-03 00:24:07 +000065/**************************************************************
66 * I2C Stuff:
67 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
68 * 0x53.
69 * Caution: on the same bus is the SPD (Serial Presens Detect
70 * EEPROM of the SDRAM
71 * The Atmel EEPROM uses 16Bit addressing.
72 ***************************************************************/
Dirk Eibach42b204f2013-04-25 02:40:01 +000073#define CONFIG_SYS_I2C
74#define CONFIG_SYS_I2C_PPC4XX
75#define CONFIG_SYS_I2C_PPC4XX_CH0
76#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
77#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +000078
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
80#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +020081#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020082#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
83#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
wdenkc6097192002-11-03 00:24:07 +000084
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
86#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenkc6097192002-11-03 00:24:07 +000087 /* 64 byte page write mode using*/
88 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +000090
91
92/***************************************************************
93 * Definitions for Serial Presence Detect EEPROM address
94 * (to get SDRAM settings)
95 ***************************************************************/
96#define SPD_EEPROM_ADDRESS 0x50
97
wdenkda55c6e2004-01-20 23:12:12 +000098#define CONFIG_BOARD_EARLY_INIT_F
David Müller2e165b52011-12-22 13:38:20 +010099#define CONFIG_BOARD_EARLY_INIT_R
100
wdenkc6097192002-11-03 00:24:07 +0000101/**************************************************************
102 * Environment definitions
103 **************************************************************/
104#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
105
106
107#define CONFIG_BOOTDELAY 5
108/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk7b4e3472005-08-13 02:04:37 +0200109/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200110#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenkc6097192002-11-03 00:24:07 +0000111
112
wdenkb02744a2003-04-05 00:53:31 +0000113#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +0000114#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
115
116#define CONFIG_IPADDR 10.0.0.100
117#define CONFIG_SERVERIP 10.0.0.1
118#define CONFIG_PREBOOT
119/***************************************************************
120 * defines if the console is stored in the environment
121 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenkc6097192002-11-03 00:24:07 +0000123/***************************************************************
124 * defines if an overwrite_console function exists
125 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
127#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenkc6097192002-11-03 00:24:07 +0000128/***************************************************************
129 * defines if the overwrite_console should be stored in the
130 * environment
131 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenkc6097192002-11-03 00:24:07 +0000133
134/**************************************************************
135 * loads config
136 *************************************************************/
137#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +0000139
wdenk2c9b05d2003-09-10 22:30:53 +0000140#define CONFIG_MISC_INIT_R
wdenkc6097192002-11-03 00:24:07 +0000141/***********************************************************
142 * Miscellaneous configurable options
143 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500145#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000147#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000149#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
155#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000156
Stefan Roese3ddce572010-09-20 16:05:31 +0200157#define CONFIG_CONS_INDEX 1 /* Use UART0 */
158#define CONFIG_SYS_NS16550
159#define CONFIG_SYS_NS16550_SERIAL
160#define CONFIG_SYS_NS16550_REG_SIZE 1
161#define CONFIG_SYS_NS16550_CLK get_serial_clock()
162
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
164#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000165
166/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc6097192002-11-03 00:24:07 +0000168 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
169 57600, 115200, 230400, 460800, 921600 }
170
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
172#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000173
wdenkc6097192002-11-03 00:24:07 +0000174/*-----------------------------------------------------------------------
175 * PCI stuff
176 *-----------------------------------------------------------------------
177 */
178#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
179#define PCI_HOST_FORCE 1 /* configure as pci host */
180#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
181
182#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000183#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc6097192002-11-03 00:24:07 +0000184#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
185#define CONFIG_PCI_PNP /* pci plug-and-play */
186 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
188#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
189#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
190#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
191#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
192#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
193#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
194#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000195
196/*-----------------------------------------------------------------------
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000200 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_SDRAM_BASE 0x00000000
202#define CONFIG_SYS_FLASH_BASE 0xFFF80000
203#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
204#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
205#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000206
207/*
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
211 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000213/*-----------------------------------------------------------------------
214 * FLASH organization
215 */
David Müller2e165b52011-12-22 13:38:20 +0100216#define CONFIG_SYS_UPDATE_FLASH_SIZE
217#define CONFIG_SYS_FLASH_PROTECTION
218#define CONFIG_SYS_FLASH_EMPTY_INFO
219
220#define CONFIG_SYS_FLASH_CFI
221#define CONFIG_FLASH_CFI_DRIVER
222
223#define CONFIG_FLASH_SHOW_PROGRESS 45
wdenkc6097192002-11-03 00:24:07 +0000224
David Müller2e165b52011-12-22 13:38:20 +0100225#define CONFIG_SYS_MAX_FLASH_BANKS 1
226#define CONFIG_SYS_MAX_FLASH_SECT 256
wdenkc6097192002-11-03 00:24:07 +0000227
wdenkc6097192002-11-03 00:24:07 +0000228/*
229 * Init Memory Controller:
230 */
wdenk2c9b05d2003-09-10 22:30:53 +0000231#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
232#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
233/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
234#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000235
wdenkda55c6e2004-01-20 23:12:12 +0000236#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000237
238/* Configuration Port location */
239#define CONFIG_PORT_ADDR 0xF4000000
240#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
241
242
wdenkc6097192002-11-03 00:24:07 +0000243/*-----------------------------------------------------------------------
244 * Definitions for initial stack pointer and data area (in On Chip SRAM)
245 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_TEMP_STACK_OCM 1
247#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
248#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
249#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200250#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200251#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000253
wdenkc6097192002-11-03 00:24:07 +0000254/***********************************************************************
255 * External peripheral base address
256 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenkc6097192002-11-03 00:24:07 +0000258
259/***********************************************************************
260 * Last Stage Init
261 ***********************************************************************/
262#define CONFIG_LAST_STAGE_INIT
263/************************************************************
264 * Ethernet Stuff
265 ***********************************************************/
Ben Warren3a918a62008-10-27 23:50:15 -0700266#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +0000267#define CONFIG_MII 1 /* MII PHY management */
268#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenkc6097192002-11-03 00:24:07 +0000269/************************************************************
270 * RTC
271 ***********************************************************/
272#define CONFIG_RTC_MC146818
273#undef CONFIG_WATCHDOG /* watchdog disabled */
274
275/************************************************************
276 * IDE/ATA stuff
277 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
279#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000280
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200281#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
282#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
283#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
284#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
285#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
286#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenkc6097192002-11-03 00:24:07 +0000287
288#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
289#undef CONFIG_IDE_LED /* no led for ide supported */
290#define CONFIG_IDE_RESET /* reset for ide supported... */
291#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk2c9b05d2003-09-10 22:30:53 +0000292#define CONFIG_SUPPORT_VFAT
wdenkc6097192002-11-03 00:24:07 +0000293
294/************************************************************
295 * ATAPI support (experimental)
296 ************************************************************/
297#define CONFIG_ATAPI /* enable ATAPI Support */
298
299/************************************************************
300 * SCSI support (experimental) only SYM53C8xx supported
301 ************************************************************/
302#define CONFIG_SCSI_SYM53C8XX
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
304#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
305#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
306#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
wdenkc6097192002-11-03 00:24:07 +0000307
308/************************************************************
309 * Disk-On-Chip configuration
310 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200311#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
312#define CONFIG_SYS_DOC_SHORT_TIMEOUT
313#define CONFIG_SYS_DOC_SUPPORT_2000
314#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
wdenkc6097192002-11-03 00:24:07 +0000315
316/************************************************************
317 * DISK Partition support
318 ************************************************************/
319#define CONFIG_DOS_PARTITION
320#define CONFIG_MAC_PARTITION
321#define CONFIG_ISO_PARTITION /* Experimental */
322
323/************************************************************
324 * Keyboard support
325 ************************************************************/
326#define CONFIG_ISA_KEYBOARD
327
328/************************************************************
329 * Video support
330 ************************************************************/
331#define CONFIG_VIDEO /*To enable video controller support */
332#define CONFIG_VIDEO_CT69000
333#define CONFIG_CFB_CONSOLE
334#define CONFIG_VIDEO_LOGO
335#define CONFIG_CONSOLE_EXTRA_INFO
336#define CONFIG_VGA_AS_SINGLE_DEVICE
337#define CONFIG_VIDEO_SW_CURSOR
338#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
339
340/************************************************************
341 * USB support
342 ************************************************************/
343#define CONFIG_USB_UHCI
344#define CONFIG_USB_KEYBOARD
345#define CONFIG_USB_STORAGE
346
347/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD2a7a0312009-05-16 12:14:54 +0200348#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenkc6097192002-11-03 00:24:07 +0000349
350/************************************************************
351 * Debug support
352 ************************************************************/
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500353#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000354#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenkc6097192002-11-03 00:24:07 +0000355#endif
356
357/************************************************************
wdenk4ea537d2003-12-07 18:32:37 +0000358 * support BZIP2 compression
359 ************************************************************/
360#define CONFIG_BZIP2 1
361
362/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000363 * Ident
364 ************************************************************/
365#define VERSION_TAG "released"
wdenke39c2842003-06-04 15:05:30 +0000366#define CONFIG_ISO_STRING "MEV-10066-001"
367#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
wdenkc6097192002-11-03 00:24:07 +0000368
369
370#endif /* __CONFIG_H */