blob: 413a698511bda34d77f30e26f1f95eed00da3c38 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
York Sun7b08d212014-06-23 15:15:56 -07002/*
3 * Copyright 2014 Freescale Semiconductor
York Sun7b08d212014-06-23 15:15:56 -07004 */
5#include <common.h>
6#include <malloc.h>
7#include <errno.h>
8#include <netdev.h>
9#include <fsl_ifc.h>
10#include <fsl_ddr.h>
11#include <asm/io.h>
12#include <fdt_support.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090013#include <linux/libfdt.h>
J. German Rivera43e4ae32015-01-06 13:19:02 -080014#include <fsl-mc/fsl_mc.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060015#include <env_internal.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080016#include <asm/arch/soc.h>
York Sun7b08d212014-06-23 15:15:56 -070017
18DECLARE_GLOBAL_DATA_PTR;
19
20int board_init(void)
21{
22 init_final_memctl_regs();
Prabhakar Kushwahacf329182014-07-14 17:15:44 +053023
24#ifdef CONFIG_ENV_IS_NOWHERE
25 gd->env_addr = (ulong)&default_environment[0];
26#endif
27
York Sun7b08d212014-06-23 15:15:56 -070028 return 0;
29}
30
31int board_early_init_f(void)
32{
Scott Woodf64c98c2015-03-20 19:28:12 -070033 fsl_lsch3_early_init_f();
York Sun7b08d212014-06-23 15:15:56 -070034 return 0;
35}
36
York Sunc7a0e302014-08-13 10:21:05 -070037void detail_board_ddr_info(void)
38{
39 puts("\nDDR ");
40 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
41 print_ddr_info(0);
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053042#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Suncbe8e1c2016-04-04 11:41:26 -070043 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
York Sunc7a0e302014-08-13 10:21:05 -070044 puts("\nDP-DDR ");
45 print_size(gd->bd->bi_dram[2].size, "");
46 print_ddr_info(CONFIG_DP_DDR_CTRL);
47 }
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053048#endif
York Sunc7a0e302014-08-13 10:21:05 -070049}
50
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070051#if defined(CONFIG_ARCH_MISC_INIT)
52int arch_misc_init(void)
53{
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070054 return 0;
55}
56#endif
57
York Sun7b08d212014-06-23 15:15:56 -070058int board_eth_init(bd_t *bis)
59{
60 int error = 0;
61
62#ifdef CONFIG_SMC91111
63 error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
64#endif
65
Santan Kumar1afa9002017-05-05 15:42:29 +053066#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -070067 error = cpu_eth_init(bis);
68#endif
69 return error;
70}
71
Santan Kumar1afa9002017-05-05 15:42:29 +053072#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -070073void fdt_fixup_board_enet(void *fdt)
74{
75 int offset;
76
Stuart Yodera3466152016-03-02 16:37:13 -060077 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
J. German Rivera43e4ae32015-01-06 13:19:02 -080078
79 /*
80 * TODO: Remove this when backward compatibility
Stuart Yodera3466152016-03-02 16:37:13 -060081 * with old DT node (/fsl-mc) is no longer needed.
J. German Rivera43e4ae32015-01-06 13:19:02 -080082 */
83 if (offset < 0)
Stuart Yodera3466152016-03-02 16:37:13 -060084 offset = fdt_path_offset(fdt, "/fsl-mc");
J. German Rivera43e4ae32015-01-06 13:19:02 -080085
86 if (offset < 0) {
87 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
88 __func__, offset);
89 return;
90 }
91
Mian Yousaf Kaukab97124652018-12-18 14:01:17 +010092 if (get_mc_boot_status() == 0 &&
93 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
York Sun7b08d212014-06-23 15:15:56 -070094 fdt_status_okay(fdt, offset);
95 else
96 fdt_status_fail(fdt, offset);
97}
Alexander Graf2ebeb442016-11-17 01:02:57 +010098
99void board_quiesce_devices(void)
100{
101 fsl_mc_ldpaa_exit(gd->bd);
102}
York Sun7b08d212014-06-23 15:15:56 -0700103#endif
104
105#ifdef CONFIG_OF_BOARD_SETUP
Simon Glass2aec3cc2014-10-23 18:58:47 -0600106int ft_board_setup(void *blob, bd_t *bd)
York Sun7b08d212014-06-23 15:15:56 -0700107{
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530108 u64 base[CONFIG_NR_DRAM_BANKS];
109 u64 size[CONFIG_NR_DRAM_BANKS];
York Sun7b08d212014-06-23 15:15:56 -0700110
York Sun290a83a2014-09-08 12:20:01 -0700111 ft_cpu_setup(blob, bd);
112
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530113 /* fixup DT for the two GPP DDR banks */
114 base[0] = gd->bd->bi_dram[0].start;
115 size[0] = gd->bd->bi_dram[0].size;
116 base[1] = gd->bd->bi_dram[1].start;
117 size[1] = gd->bd->bi_dram[1].size;
118
York Sun4de24ef2017-03-06 09:02:28 -0800119#ifdef CONFIG_RESV_RAM
120 /* reduce size if reserved memory is within this bank */
121 if (gd->arch.resv_ram >= base[0] &&
122 gd->arch.resv_ram < base[0] + size[0])
123 size[0] = gd->arch.resv_ram - base[0];
124 else if (gd->arch.resv_ram >= base[1] &&
125 gd->arch.resv_ram < base[1] + size[1])
126 size[1] = gd->arch.resv_ram - base[1];
127#endif
128
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530129 fdt_fixup_memory_banks(blob, base, size, 2);
York Sun7b08d212014-06-23 15:15:56 -0700130
Nipun Guptad6912642018-08-20 16:01:14 +0530131 fdt_fsl_mc_fixup_iommu_map_entry(blob);
132
Santan Kumar1afa9002017-05-05 15:42:29 +0530133#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -0700134 fdt_fixup_board_enet(blob);
135#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600136
137 return 0;
York Sun7b08d212014-06-23 15:15:56 -0700138}
139#endif
Bogdan Purcareata08bc0142017-05-24 16:40:21 +0000140
141#if defined(CONFIG_RESET_PHY_R)
142void reset_phy(void)
143{
144}
145#endif
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000146
147#ifdef CONFIG_TFABOOT
148void *env_sf_get_env_addr(void)
149{
150 return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
151}
152#endif