| Parthiban Nallathambi | c466938 | 2019-04-10 16:35:32 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com> |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
| 8 | #include "imx6ull.dtsi" |
| 9 | #include "pcl063-common.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "Phytec phyBOARD-i.MX6ULL-Segin SBC"; |
| 13 | compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063", |
| 14 | "fsl,imx6ull"; |
| 15 | }; |
| 16 | |
| 17 | &i2c1 { |
| 18 | i2c_rtc: rtc@68 { |
| 19 | compatible = "microcrystal,rv4162"; |
| 20 | reg = <0x68>; |
| 21 | status = "okay"; |
| 22 | }; |
| 23 | }; |
| 24 | |
| 25 | &uart5 { |
| 26 | pinctrl-names = "default"; |
| 27 | pinctrl-0 = <&pinctrl_uart5>; |
| 28 | uart-has-rtscts; |
| 29 | status = "okay"; |
| 30 | }; |
| 31 | |
| 32 | &usdhc2 { |
| 33 | status = "okay"; |
| 34 | }; |
| 35 | |
| 36 | &usbotg1 { |
| 37 | pinctrl-names = "default"; |
| 38 | pinctrl-0 = <&pinctrl_usb_otg1_id>; |
| 39 | dr_mode = "otg"; |
| 40 | srp-disable; |
| 41 | hnp-disable; |
| 42 | adp-disable; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | |
| 46 | &usbotg2 { |
| 47 | dr_mode = "host"; |
| 48 | disable-over-current; |
| 49 | status = "okay"; |
| 50 | }; |
| 51 | |
| 52 | &iomuxc { |
| 53 | pinctrl-names = "default"; |
| 54 | |
| 55 | pinctrl_uart5: uart5grp { |
| 56 | fsl,pins = < |
| 57 | MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 |
| 58 | MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 |
| 59 | MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 |
| 60 | MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 |
| 61 | >; |
| 62 | }; |
| 63 | |
| 64 | pinctrl_usb_otg1_id: usbotg1idgrp { |
| 65 | fsl,pins = < |
| 66 | MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 |
| 67 | >; |
| 68 | }; |
| 69 | |
| 70 | }; |