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git01.mediatek.com / filogic / uboot / 3edefd50dfde40288083f7adb00e47bdc770a87b / . / arch / arm / dts / fsl-ls1028a-qds.dts
blob: 5d143ba07702e1b8bb62b64d52e04abc715fb342 [file] [log] [blame]
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP ls1028AQDS device tree source
4 *
5 * Copyright 2019 NXP
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-ls1028a.dtsi"
12
13/ {
14 model = "NXP Layerscape 1028a QDS Board";
15 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
16};
17
18&dspi0 {
19 status = "okay";
20};
21
22&dspi1 {
23 status = "okay";
24};
25
26&dspi2 {
27 status = "okay";
28};
29
30&esdhc0 {
31 status = "okay";
32};
33
34&esdhc1 {
35 status = "okay";
Alex Marginean679cd542019-08-07 19:30:03 +0300[diff] [blame]36
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]37};
38
39&i2c0 {
40 status = "okay";
Chuanhua Hanc6c006a2019-07-10 15:48:39 +0800[diff] [blame]41 u-boot,dm-pre-reloc;
42
Alex Marginean679cd542019-08-07 19:30:03 +0300[diff] [blame]43 fpga@66 {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 compatible = "simple-mfd";
47 reg = <0x66>;
48
49 mux-mdio@54 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 compatible = "mdio-mux-i2creg";
53 reg = <0x54>;
54 #mux-control-cells = <1>;
55 mux-reg-masks = <0x54 0xf0>;
56 mdio-parent-bus = <&mdio0>;
57
58 /* on-board MDIO with a single RGMII PHY */
59 mdio@00 {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 reg = <0x00>;
63
64 qds_phy0: phy@5 {
65 reg = <5>;
66 };
67 };
68 /* slot 1 */
69 slot1: mdio@40 {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 reg = <0x40>;
73 };
74 /* slot 2 */
75 slot2: mdio@50 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 reg = <0x50>;
79 };
80 /* slot 3 */
81 slot3: mdio@60 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 reg = <0x60>;
85 };
86 /* slot 4 */
87 slot4: mdio@70 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 reg = <0x70>;
91 };
92 };
93 };
94
Chuanhua Hanc6c006a2019-07-10 15:48:39 +0800[diff] [blame]95 i2c-mux@77 {
96 compatible = "nxp,pca9547";
97 reg = <0x77>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]101};
102
103&i2c1 {
104 status = "okay";
Chuanhua Han7657bc32019-07-10 15:48:40 +0800[diff] [blame]105
106 rtc@51 {
107 compatible = "pcf2127-rtc";
108 reg = <0x51>;
109 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]110};
111
112&i2c2 {
113 status = "okay";
114};
115
116&i2c3 {
117 status = "okay";
118};
119
120&i2c4 {
121 status = "okay";
122};
123
124&i2c5 {
125 status = "okay";
126};
127
128&i2c6 {
129 status = "okay";
130};
131
132&i2c7 {
133 status = "okay";
134};
135
136&sata {
137 status = "okay";
138};
139
140&serial0 {
141 status = "okay";
142};
143
144&serial1 {
145 status = "okay";
146};
147
148&usb1 {
149 status = "okay";
150};
151
152&usb2 {
153 status = "okay";
154};
Alex Marginean3be715e2019-07-03 12:11:43 +0300[diff] [blame]155
156&enetc1 {
157 status = "okay";
158 phy-mode = "rgmii";
159 phy-handle = <&qds_phy0>;
160};
161
162&mdio0 {
163 status = "okay";
Alex Marginean3be715e2019-07-03 12:11:43 +0300[diff] [blame]164};