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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schochercfcad352013-12-02 07:47:22 +01002/*
3 * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
4 * (C) Copyright 2013 Siemens AG
5 *
6 * Based on:
7 * U-Boot file: include/configs/at91sam9260ek.h
8 *
9 * (C) Copyright 2007-2008
10 * Stelian Pop <stelian@popies.net>
11 * Lead Tech Design <www.leadtechdesign.com>
Heiko Schochercfcad352013-12-02 07:47:22 +010012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
18 * SoC must be defined first, before hardware.h is included.
19 * In this case SoC is defined in boards.cfg.
20 */
21#include <asm/hardware.h>
Heiko Schocherb7773572015-08-21 18:53:46 +020022#include <linux/sizes.h>
Heiko Schochercfcad352013-12-02 07:47:22 +010023
Heiko Schochercfcad352013-12-02 07:47:22 +010024/*
25 * Warning: changing CONFIG_SYS_TEXT_BASE requires
26 * adapting the initial boot program.
27 * Since the linker has to swallow that define, we must use a pure
28 * hex number here!
29 */
30
Heiko Schochercfcad352013-12-02 07:47:22 +010031/* ARM asynchronous clock */
32#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
33#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
Heiko Schochercfcad352013-12-02 07:47:22 +010034
35/* Misc CPU related */
Heiko Schocher1af10bb2019-04-29 16:36:10 +020036
Heiko Schochercfcad352013-12-02 07:47:22 +010037#define CONFIG_USART_BASE ATMEL_BASE_DBGU
38#define CONFIG_USART_ID ATMEL_ID_SYS
Heiko Schochercfcad352013-12-02 07:47:22 +010039
Heiko Schochercfcad352013-12-02 07:47:22 +010040/*
Heiko Schochercfcad352013-12-02 07:47:22 +010041 * SDRAM: 1 bank, min 32, max 128 MB
42 * Initialized before u-boot gets started.
43 */
Heiko Schochercfcad352013-12-02 07:47:22 +010044#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
Heiko Schocher6dcb3622015-08-21 18:55:07 +020045#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
Heiko Schochercfcad352013-12-02 07:47:22 +010046
47/*
48 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
49 * leaving the correct space for initial global data structure above
50 * that address while providing maximum stack area below.
51 */
Heiko Schocher6dcb3622015-08-21 18:55:07 +020052#define CONFIG_SYS_INIT_SP_ADDR \
Heiko Schochercfcad352013-12-02 07:47:22 +010053 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
54
55/* NAND flash */
56#ifdef CONFIG_CMD_NAND
Heiko Schochercfcad352013-12-02 07:47:22 +010057#define CONFIG_SYS_MAX_NAND_DEVICE 1
58#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
59#define CONFIG_SYS_NAND_DBW_8
60#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
61#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
62#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
63#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
64#endif
65
Heiko Schochercfcad352013-12-02 07:47:22 +010066/* USB */
67#if defined(CONFIG_BOARD_TAURUS)
68#define CONFIG_USB_ATMEL
Heiko Schochercf5137c2015-09-08 11:52:52 +020069#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Heiko Schochercfcad352013-12-02 07:47:22 +010070#define CONFIG_USB_OHCI_NEW
71#define CONFIG_SYS_USB_OHCI_CPU_INIT
72#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
73#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
74#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Heiko Schochercf5137c2015-09-08 11:52:52 +020075
76/* USB DFU support */
Heiko Schochercf5137c2015-09-08 11:52:52 +020077
Heiko Schochercf5137c2015-09-08 11:52:52 +020078#define CONFIG_USB_GADGET_AT91
79
80/* DFU class support */
Heiko Schochercf5137c2015-09-08 11:52:52 +020081#define DFU_MANIFEST_POLL_TIMEOUT 25000
Heiko Schochercfcad352013-12-02 07:47:22 +010082#endif
83
Heiko Schocher398b45b2014-10-31 08:30:56 +010084/* SPI EEPROM */
Heiko Schocher398b45b2014-10-31 08:30:56 +010085#define TAURUS_SPI_MASK (1 << 4)
Heiko Schocher398b45b2014-10-31 08:30:56 +010086
Heiko Schocher6f2a3252014-11-18 09:41:58 +010087#if defined(CONFIG_SPL_BUILD)
88/* SPL related */
Heiko Schocher6f2a3252014-11-18 09:41:58 +010089#endif
90
Heiko Schochercfcad352013-12-02 07:47:22 +010091/* bootstrap in spi flash , u-boot + env + linux in nandflash */
Heiko Schocherb7773572015-08-21 18:53:46 +020092
Heiko Schocher1af10bb2019-04-29 16:36:10 +020093#ifndef CONFIG_SPL_BUILD
94#if defined(CONFIG_BOARD_AXM)
95#define CONFIG_EXTRA_ENV_SETTINGS \
96 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
97 "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \
98 "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \
99 "boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \
100 "boot_retries=0\0" \
101 "ethact=macb0\0" \
102 "flash_nfs=run nand_kernel;run nfsargs;run addip;" \
103 "upgrade_available;bootm ${kernel_ram};reset\0" \
104 "flash_self=run nand_kernel;run setbootargs;upgrade_available;" \
105 "bootm ${kernel_ram};reset\0" \
106 "flash_self_test=run nand_kernel;run setbootargs addtest;" \
107 "upgrade_available;bootm ${kernel_ram};reset\0" \
108 "hostname=systemone\0" \
109 "kernel_Off=0x00200000\0" \
110 "kernel_Off_fallback=0x03800000\0" \
111 "kernel_ram=0x21500000\0" \
112 "kernel_size=0x00400000\0" \
113 "kernel_size_fallback=0x00400000\0" \
114 "loads_echo=1\0" \
115 "nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \
116 "${kernel_size}\0" \
117 "net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \
118 "run nfsargs;run addip;upgrade_available;" \
119 "bootm ${kernel_ram};reset\0" \
120 "netdev=eth0\0" \
121 "nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs " \
122 "rw nfsroot=${serverip}:${rootpath} " \
123 "at91sam9_wdt.wdt_timeout=16\0" \
124 "partitionset_active=A\0" \
125 "preboot=echo;echo Type 'run flash_self' to use kernel and root " \
126 "filesystem on memory;echo Type 'run flash_nfs' to use " \
127 "kernel from memory and root filesystem over NFS;echo Type " \
128 "'run net_nfs' to get Kernel over TFTP and mount root " \
129 "filesystem over NFS;echo\0" \
130 "project_dir=systemone\0" \
131 "root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0" \
132 "rootfs=/dev/mtdblock5\0" \
133 "rootfs_fallback=/dev/mtdblock7\0" \
134 "setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops " \
135 "root=${rootfs} rootfstype=jffs2 panic=7 " \
136 "at91sam9_wdt.wdt_timeout=16\0" \
137 "stderr=serial\0" \
138 "stdin=serial\0" \
139 "stdout=serial\0" \
140 "upgrade_available=0\0"
141#endif
142#endif /* #ifndef CONFIG_SPL_BUILD */
Heiko Schochercfcad352013-12-02 07:47:22 +0100143
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100144/* Defines for SPL */
Heiko Schocherb7773572015-08-21 18:53:46 +0200145#define CONFIG_SPL_MAX_SIZE (31 * SZ_512)
146#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K)
Heiko Schocher6f2a3252014-11-18 09:41:58 +0100147#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
148 CONFIG_SYS_MALLOC_LEN)
149#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100150
151#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
Heiko Schocher6dcb3622015-08-21 18:55:07 +0200152#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512)
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100153
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100154#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100155#define CONFIG_SPL_NAND_RAW_ONLY
156#define CONFIG_SPL_NAND_SOFTECC
Heiko Schochercf5137c2015-09-08 11:52:52 +0200157#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100158#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
159#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100160
Heiko Schocher6dcb3622015-08-21 18:55:07 +0200161#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100162#define CONFIG_SYS_NAND_ECCSIZE 256
163#define CONFIG_SYS_NAND_ECCBYTES 3
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100164#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
165 48, 49, 50, 51, 52, 53, 54, 55, \
166 56, 57, 58, 59, 60, 61, 62, 63, }
167
Heiko Schocher5453c6c2014-10-31 08:31:05 +0100168#define CONFIG_SYS_MASTER_CLOCK 132096000
169#define AT91_PLL_LOCK_TIMEOUT 1000000
170#define CONFIG_SYS_AT91_PLLA 0x202A3F01
171#define CONFIG_SYS_MCKR 0x1300
172#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
173#define CONFIG_SYS_AT91_PLLB 0x10193F05
Heiko Schocherb7773572015-08-21 18:53:46 +0200174
Stefan Roese67bcbef2019-04-02 10:57:25 +0200175#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
176#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
177
Heiko Schochercfcad352013-12-02 07:47:22 +0100178#endif