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git01.mediatek.com / filogic / uboot / 3ebef53a9339daa334d76a71379511b15f31ec31 / . / include / configs / exynos-common.h
blob: dd1cbd7ab84d40476bb9ed95079289c9f28b8e9a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]2/*
3 * Copyright (C) 2013 Samsung Electronics
4 *
5 * Common configuration settings for the SAMSUNG EXYNOS boards.
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]6 */
7
8#ifndef __EXYNOS_COMMON_H
9#define __EXYNOS_COMMON_H
10
11/* High Level Configuration Options */
12#define CONFIG_SAMSUNG /* in a SAMSUNG core */
13#define CONFIG_S5P /* S5P Family */
14
15#include <asm/arch/cpu.h> /* get chip and board defs */
16#include <linux/sizes.h>
Simon Glassfb64e362020-05-10 11:40:09 -0600[diff] [blame]17#include <linux/stringify.h>
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]18
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]19/* Keep L2 Cache Disabled */
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]20
21/* input clock of PLL: 24MHz input clock */
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]22
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]23/* select serial console configuration */
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]24
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]25/* PWM */
26#define CONFIG_PWM
27
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]28/* Miscellaneous configurable options */
Ian Campbellaf36fc32014-11-09 10:44:33 +0000[diff] [blame]29#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
30#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]31
32/* Boot Argument Buffer Size */
33#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
34
Simon Glass14e27ab2014-10-07 22:01:45 -0600[diff] [blame]35#endif /* __CONFIG_H */