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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 *
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020011 */
12
13#include <common.h>
Simon Glassdb229612019-08-01 09:46:42 -060014#include <env.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020015#include <pci.h>
16#include <asm/processor.h>
17#include <asm/immap_85xx.h>
18#include <ioports.h>
19#include <flash.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090020#include <linux/libfdt.h>
Sergei Poselenov09842c52008-05-07 15:10:49 +020021#include <fdt_support.h>
Andy Fleming7109ea32008-06-10 18:49:34 -050022#include <asm/io.h>
u-boot@bugs.denx.debbab0bc2008-09-11 15:40:01 +020023#include <i2c.h>
24#include <mb862xx.h>
25#include <video_fb.h>
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020026#include "upm_table.h"
Detlev Zundel0244f672008-08-15 15:42:12 +020027
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020028DECLARE_GLOBAL_DATA_PTR;
29
30extern flash_info_t flash_info[]; /* FLASH chips info */
u-boot@bugs.denx.debbab0bc2008-09-11 15:40:01 +020031extern GraphicDevice mb862xx;
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020032
33void local_bus_init (void);
34ulong flash_get_size (ulong base, int banknum);
35
36int checkboard (void)
37{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000039 char buf[64];
Sergei Poselenove13be1a2008-05-27 13:47:00 +020040 int f;
Simon Glass64b723f2017-08-03 12:22:12 -060041 int i = env_get_f("serial#", buf, sizeof(buf));
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000042#ifdef CONFIG_PCI
43 char *src;
44#endif
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020045
46 puts("Board: Socrates");
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000047 if (i > 0) {
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020048 puts(", serial# ");
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000049 puts(buf);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020050 }
51 putc('\n');
52
Heiko Schocher84cdae22019-10-16 05:55:54 +020053#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
Andy Fleming7109ea32008-06-10 18:49:34 -050054 /* Check the PCI_clk sel bit */
55 if (in_be32(&gur->porpllsr) & (1<<15)) {
Sergei Poselenove13be1a2008-05-27 13:47:00 +020056 src = "SYSCLK";
57 f = CONFIG_SYS_CLK_FREQ;
58 } else {
59 src = "PCI_CLK";
60 f = CONFIG_PCI_CLK_FREQ;
61 }
62 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020063#else
64 printf ("PCI1: disabled\n");
65#endif
66
67 /*
68 * Initialize local bus.
69 */
70 local_bus_init ();
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020071 return 0;
72}
73
74int misc_init_r (void)
75{
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020076 /*
77 * Adjust flash start and offset to detected values
78 */
79 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
80 gd->bd->bi_flashoffset = 0;
81
82 /*
83 * Check if boot FLASH isn't max size
84 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
Becky Bruce0d4cee12010-06-17 11:37:20 -050086 set_lbc_or(0, gd->bd->bi_flashstart |
87 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
88 set_lbc_br(0, gd->bd->bi_flashstart |
89 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020090
91 /*
92 * Re-check to get correct base address
93 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020095 }
96
97 /*
98 * Check if only one FLASH bank is available
99 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
Becky Bruce0d4cee12010-06-17 11:37:20 -0500101 set_lbc_or(1, 0);
102 set_lbc_br(1, 0);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200103
104 /*
105 * Re-do flash protection upon new addresses
106 */
107 flash_protect (FLAG_PROTECT_CLEAR,
108 gd->bd->bi_flashstart, 0xffffffff,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200110
111 /* Monitor protection ON by default */
112 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
114 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200115
116 /* Environment protection ON by default */
117 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200118 CONFIG_ENV_ADDR,
119 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200121
122 /* Redundant environment protection ON by default */
123 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200124 CONFIG_ENV_ADDR_REDUND,
Wolfgang Denk47913832009-05-15 00:16:03 +0200125 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200127 }
128
Heiko Schocher84cdae22019-10-16 05:55:54 +0200129#if defined(CONFIG_DM_PCI)
130 pci_init();
131#endif
132
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200133 return 0;
134}
135
136/*
137 * Initialize Local Bus
138 */
139void local_bus_init (void)
140{
Becky Bruce0d4cee12010-06-17 11:37:20 -0500141 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Detlev Zundel0244f672008-08-15 15:42:12 +0200143 sys_info_t sysinfo;
144 uint clkdiv;
145 uint lbc_mhz;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146 uint lcrr = CONFIG_SYS_LBC_LCRR;
Detlev Zundel0244f672008-08-15 15:42:12 +0200147
148 get_sys_info (&sysinfo);
Trent Piepho1b560ac2008-12-03 15:16:34 -0800149 clkdiv = lbc->lcrr & LCRR_CLKDIV;
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530150 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
Detlev Zundel0244f672008-08-15 15:42:12 +0200151
152 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
153 if (lbc_mhz >= 66)
154 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
155 else
156 lcrr |= LCRR_DBYP; /* DLL Bypass */
157
158 out_be32 (&lbc->lcrr, lcrr);
159 asm ("sync;isync;msync");
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200160
Detlev Zundel0244f672008-08-15 15:42:12 +0200161 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
162 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
163 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
164 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200165
Detlev Zundel0244f672008-08-15 15:42:12 +0200166 /* Init UPMA for FPGA access */
167 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
168 upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200169
u-boot@bugs.denx.debbab0bc2008-09-11 15:40:01 +0200170 /* Init UPMB for Lime controller access */
171 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
172 upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200173}
174
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200175#ifdef CONFIG_BOARD_EARLY_INIT_R
176int board_early_init_r (void)
177{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Detlev Zundel0244f672008-08-15 15:42:12 +0200179
180 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
181 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
182 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
183 udelay(200);
184 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
185
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200186 return (0);
187}
188#endif /* CONFIG_BOARD_EARLY_INIT_R */
Sergei Poselenov09842c52008-05-07 15:10:49 +0200189
Robert P. J. Day3c757002016-05-19 15:23:12 -0400190#ifdef CONFIG_OF_BOARD_SETUP
Simon Glass2aec3cc2014-10-23 18:58:47 -0600191int ft_board_setup(void *blob, bd_t *bd)
Sergei Poselenov09842c52008-05-07 15:10:49 +0200192{
Detlev Zundel0244f672008-08-15 15:42:12 +0200193 u32 val[12];
194 int rc, i = 0;
Sergei Poselenov09842c52008-05-07 15:10:49 +0200195
196 ft_cpu_setup(blob, bd);
197
Detlev Zundel0244f672008-08-15 15:42:12 +0200198 /* Fixup NOR FLASH mapping */
199 val[i++] = 0; /* chip select number */
200 val[i++] = 0; /* always 0 */
201 val[i++] = gd->bd->bi_flashstart;
202 val[i++] = gd->bd->bi_flashsize;
Sergei Poselenov09842c52008-05-07 15:10:49 +0200203
Heiko Schocherff109932019-10-16 05:55:51 +0200204#if defined(CONFIG_VIDEO_MB862xx)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200206 /* Fixup LIME mapping */
207 val[i++] = 2; /* chip select number */
208 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209 val[i++] = CONFIG_SYS_LIME_BASE;
210 val[i++] = CONFIG_SYS_LIME_SIZE;
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200211 }
Heiko Schocherff109932019-10-16 05:55:51 +0200212#endif
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200213
Detlev Zundel0244f672008-08-15 15:42:12 +0200214 /* Fixup FPGA mapping */
215 val[i++] = 3; /* chip select number */
216 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217 val[i++] = CONFIG_SYS_FPGA_BASE;
218 val[i++] = CONFIG_SYS_FPGA_SIZE;
Sergei Poselenovbc3d08d2008-06-06 15:42:45 +0200219
Detlev Zundel0244f672008-08-15 15:42:12 +0200220 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
221 val, i * sizeof(u32), 1);
Sergei Poselenovbc3d08d2008-06-06 15:42:45 +0200222 if (rc)
Detlev Zundel0244f672008-08-15 15:42:12 +0200223 printf("Unable to update localbus ranges, err=%s\n",
Sergei Poselenovbc3d08d2008-06-06 15:42:45 +0200224 fdt_strerror(rc));
Simon Glass2aec3cc2014-10-23 18:58:47 -0600225
226 return 0;
Sergei Poselenov09842c52008-05-07 15:10:49 +0200227}
Robert P. J. Day3c757002016-05-19 15:23:12 -0400228#endif /* CONFIG_OF_BOARD_SETUP */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200229
Heiko Schocher66daf322019-10-16 05:55:49 +0200230#if defined(CONFIG_OF_SEPARATE)
231void *board_fdt_blob_setup(void)
232{
233 void *fw_dtb;
234
235 fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
236 if (fdt_magic(fw_dtb) != FDT_MAGIC) {
237 printf("DTB is not passed via %x\n", (u32)fw_dtb);
238 return NULL;
239 }
240
241 return fw_dtb;
242}
243#endif
Heiko Schocher08ce3722019-10-16 05:55:53 +0200244
245int get_serial_clock(void)
246{
247 return 333333330;
248}