| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Angelo Dureghello | 89ae64c | 2017-05-14 21:42:27 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Board-specific sbf ddr/sdram init. |
| 4 | * |
| 5 | * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> |
| Angelo Dureghello | 89ae64c | 2017-05-14 21:42:27 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | .global sbf_dram_init |
| 9 | .text |
| 10 | |
| 11 | sbf_dram_init: |
| 12 | move.l #0xFC04002D, %a1 |
| 13 | move.b #46, (%a1) /* DDR */ |
| 14 | |
| 15 | /* slew settings */ |
| 16 | move.l #0xEC094060, %a1 |
| 17 | move.b #0, (%a1) |
| 18 | |
| 19 | /* use vco instead of cpu*2 clock for ddr clock */ |
| 20 | move.l #0xEC09001A, %a1 |
| 21 | move.w #0xE01D, (%a1) |
| 22 | |
| 23 | /* DDR settings */ |
| 24 | move.l #0xFC0B8180, %a1 |
| 25 | move.l #0x00000000, (%a1) |
| 26 | move.l #0x40000000, (%a1) |
| 27 | |
| 28 | move.l #0xFC0B81AC, %a1 |
| 29 | move.l #0x01030203, (%a1) |
| 30 | |
| 31 | move.l #0xFC0B8000, %a1 |
| 32 | move.l #0x01010101, (%a1)+ /* 0x00 */ |
| 33 | move.l #0x00000101, (%a1)+ /* 0x04 */ |
| 34 | move.l #0x01010100, (%a1)+ /* 0x08 */ |
| 35 | move.l #0x01010000, (%a1)+ /* 0x0C */ |
| 36 | move.l #0x00010101, (%a1)+ /* 0x10 */ |
| 37 | move.l #0xFC0B8018, %a1 |
| 38 | move.l #0x00010100, (%a1)+ /* 0x18 */ |
| 39 | move.l #0x00000001, (%a1)+ /* 0x1C */ |
| 40 | move.l #0x01000001, (%a1)+ /* 0x20 */ |
| 41 | move.l #0x00000100, (%a1)+ /* 0x24 */ |
| 42 | move.l #0x00010001, (%a1)+ /* 0x28 */ |
| 43 | move.l #0x00000200, (%a1)+ /* 0x2C */ |
| 44 | move.l #0x01000002, (%a1)+ /* 0x30 */ |
| 45 | move.l #0x00000000, (%a1)+ /* 0x34 */ |
| 46 | move.l #0x00000100, (%a1)+ /* 0x38 */ |
| 47 | move.l #0x02000100, (%a1)+ /* 0x3C */ |
| 48 | move.l #0x02000407, (%a1)+ /* 0x40 */ |
| 49 | move.l #0x02030007, (%a1)+ /* 0x44 */ |
| 50 | move.l #0x02000100, (%a1)+ /* 0x48 */ |
| 51 | move.l #0x0A030203, (%a1)+ /* 0x4C */ |
| 52 | move.l #0x00020708, (%a1)+ /* 0x50 */ |
| 53 | move.l #0x00050008, (%a1)+ /* 0x54 */ |
| 54 | move.l #0x04030002, (%a1)+ /* 0x58 */ |
| 55 | move.l #0x00000004, (%a1)+ /* 0x5C */ |
| 56 | move.l #0x020A0000, (%a1)+ /* 0x60 */ |
| 57 | move.l #0x0C00000E, (%a1)+ /* 0x64 */ |
| 58 | move.l #0x00002004, (%a1)+ /* 0x68 */ |
| 59 | move.l #0x00000000, (%a1)+ /* 0x6C */ |
| 60 | move.l #0x00100010, (%a1)+ /* 0x70 */ |
| 61 | move.l #0x00100010, (%a1)+ /* 0x74 */ |
| 62 | move.l #0x00000000, (%a1)+ /* 0x78 */ |
| 63 | move.l #0x07990000, (%a1)+ /* 0x7C */ |
| 64 | move.l #0xFC0B80A0, %a1 |
| 65 | move.l #0x00000000, (%a1)+ /* 0xA0 */ |
| 66 | move.l #0x00C80064, (%a1)+ /* 0xA4 */ |
| 67 | move.l #0x44520002, (%a1)+ /* 0xA8 */ |
| 68 | move.l #0x00C80023, (%a1)+ /* 0xAC */ |
| 69 | move.l #0xFC0B80B4, %a1 |
| 70 | move.l #0x0000C350, (%a1) /* 0xB4 */ |
| 71 | move.l #0xFC0B80E0, %a1 |
| 72 | move.l #0x04000000, (%a1)+ /* 0xE0 */ |
| 73 | move.l #0x03000304, (%a1)+ /* 0xE4 */ |
| 74 | move.l #0x40040000, (%a1)+ /* 0xE8 */ |
| 75 | move.l #0xC0004004, (%a1)+ /* 0xEC */ |
| 76 | move.l #0x0642C000, (%a1)+ /* 0xF0 */ |
| 77 | move.l #0x00000642, (%a1)+ /* 0xF4 */ |
| 78 | move.l #0xFC0B8024, %a1 |
| 79 | tpf |
| 80 | move.l #0x01000100, (%a1) /* 0x24 */ |
| 81 | |
| 82 | move.l #0x2000, %d1 |
| 83 | bsr asm_delay |
| 84 | |
| 85 | rts |