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git01.mediatek.com / filogic / uboot / 3e7fd6f57c1a5f488a44e3a4e91c628e6e8065fd / . / board / amcc / kilauea / chip_config.c
blob: 7e9dd3b5cd8d647859a740467620d208399ed449 [file] [log] [blame]
Stefan Roese142a2e62009-07-21 14:06:29 +0200[diff] [blame]1/*
2 * (C) Copyright 2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese142a2e62009-07-21 14:06:29 +0200[diff] [blame]6 */
7
8#include <common.h>
9#include <asm/ppc4xx_config.h>
10
Stefan Roese9b89d302009-07-27 07:42:48 +0200[diff] [blame]11/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
12
Stefan Roese142a2e62009-07-21 14:06:29 +0200[diff] [blame]13struct ppc4xx_config ppc4xx_config_val[] = {
14 {
15 "333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
16 {
17 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
18 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
19 }
20 },
21 {
22 "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
23 {
24 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
25 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
26 }
27 },
28 {
29 "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
30 {
31 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
32 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
33 }
34 },
35 {
36 "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
Stefan Roese9b89d302009-07-27 07:42:48 +0200[diff] [blame]37 {
38 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
39 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
40 }
Stefan Roese142a2e62009-07-21 14:06:29 +0200[diff] [blame]41 },
42 {
Stefan Roese9b89d302009-07-27 07:42:48 +0200[diff] [blame]43 "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
44 {
45 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
46 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
47 }
48 },
49 {
Stefan Roese142a2e62009-07-21 14:06:29 +0200[diff] [blame]50 "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
51 {
52 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
53 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
54 }
55 },
56 {
Stefan Roese9b89d302009-07-27 07:42:48 +0200[diff] [blame]57 "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
58 {
59 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
60 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
61 }
62 },
63 {
Stefan Roese142a2e62009-07-21 14:06:29 +0200[diff] [blame]64 "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
65 {
66 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
67 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
68 }
69 },
70};
71
72int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);