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git01.mediatek.com / filogic / uboot / 3e2b61ceae5edaf34bb8dade82dc352b4932e917 / . / drivers / ddr / microchip / ddr2_regs.h
blob: 0f4b159048c82e873872d74f579107775707e282 [file] [log] [blame]
Purna Chandra Mandale80d11f2016-01-28 15:30:15 +0530[diff] [blame]1/*
2 * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 */
7
8#ifndef __MICROCHIP_DDR2_REGS_H
9#define __MICROCHIP_DDR2_REGS_H
10
11#include <linux/bitops.h>
12
13/* DDR2 Controller */
14struct ddr2_ctrl_regs {
15 u32 tsel;
16 u32 minlim;
17 u32 reqprd;
18 u32 mincmd;
19 u32 memcon;
20 u32 memcfg0;
21 u32 memcfg1;
22 u32 memcfg2;
23 u32 memcfg3;
24 u32 memcfg4;
25 u32 refcfg;
26 u32 pwrcfg;
27 u32 dlycfg0;
28 u32 dlycfg1;
29 u32 dlycfg2;
30 u32 dlycfg3;
31 u32 odtcfg;
32 u32 xfercfg;
33 u32 cmdissue;
34 u32 odtencfg;
35 u32 memwidth;
36 u32 unused[11];
37 u32 cmd10[16];
38 u32 cmd20[16];
39};
40
41/* Arbiter Config */
42#define MIN_LIM_WIDTH 5
43#define RQST_PERIOD_WIDTH 8
44#define MIN_CMDACPT_WIDTH 8
45
46/* Refresh Config */
47#define REFCNT_CLK(x) (x)
48#define REFDLY_CLK(x) ((x) << 16)
49#define MAX_PEND_REF(x) ((x) << 24)
50
51/* Power Config */
52#define PRECH_PWR_DN_ONLY(x) ((x) << 22)
53#define SELF_REF_DLY(x) ((x) << 12)
54#define PWR_DN_DLY(x) ((x) << 4)
55#define EN_AUTO_SELF_REF(x) ((x) << 3)
56#define EN_AUTO_PWR_DN(x) ((x) << 2)
57#define ERR_CORR_EN(x) ((x) << 1)
58#define ECC_EN(x) (x)
59
60/* Memory Width */
61#define HALF_RATE_MODE BIT(3)
62
63/* Delay Config */
64#define ODTWLEN(x) ((x) << 20)
65#define ODTRLEN(x) ((x) << 16)
66#define ODTWDLY(x) ((x) << 12)
67#define ODTRDLY(x) ((x) << 8)
68
69/* Xfer Config */
70#define BIG_ENDIAN(x) ((x) << 31)
71#define MAX_BURST(x) ((x) << 24)
72#define RDATENDLY(x) ((x) << 16)
73#define NXDATAVDLY(x) ((x) << 4)
74#define NXTDATRQDLY(x) ((x) << 0)
75
76/* Host Commands */
77#define IDLE_NOP 0x00ffffff
78#define PRECH_ALL_CMD 0x00fff401
79#define REF_CMD 0x00fff801
80#define LOAD_MODE_CMD 0x00fff001
81#define CKE_LOW 0x00ffeffe
82
83#define NUM_HOST_CMDS 12
84
85/* Host CMD Issue */
86#define CMD_VALID BIT(4)
87#define NUMHOSTCMD(x) (x)
88
89/* Memory Control */
90#define INIT_DONE BIT(1)
91#define INIT_START BIT(0)
92
93/* Address Control */
94#define EN_AUTO_PRECH 0
95#define SB_PRI 1
96
97/* DDR2 Phy Register */
98struct ddr2_phy_regs {
99 u32 scl_start;
100 u32 unused1[2];
101 u32 scl_latency;
102 u32 unused2[2];
103 u32 scl_config_1;
104 u32 scl_config_2;
105 u32 pad_ctrl;
106 u32 dll_recalib;
107};
108
109/* PHY PAD CONTROL */
110#define ODT_SEL BIT(0)
111#define ODT_EN BIT(1)
112#define DRIVE_SEL(x) ((x) << 2)
113#define ODT_PULLDOWN(x) ((x) << 4)
114#define ODT_PULLUP(x) ((x) << 6)
115#define EXTRA_OEN_CLK(x) ((x) << 8)
116#define NOEXT_DLL BIT(9)
117#define DLR_DFT_WRCMD BIT(13)
118#define HALF_RATE BIT(14)
119#define DRVSTR_PFET(x) ((x) << 16)
120#define DRVSTR_NFET(x) ((x) << 20)
121#define RCVR_EN BIT(28)
122#define PREAMBLE_DLY(x) ((x) << 29)
123
124/* PHY DLL RECALIBRATE */
125#define RECALIB_CNT(x) ((x) << 8)
126#define DISABLE_RECALIB(x) ((x) << 26)
127#define DELAY_START_VAL(x) ((x) << 28)
128
129/* PHY SCL CONFIG1 */
130#define SCL_BURST8 BIT(0)
131#define SCL_DDR_CONNECTED BIT(1)
132#define SCL_RCAS_LAT(x) ((x) << 4)
133#define SCL_ODTCSWW BIT(24)
134
135/* PHY SCL CONFIG2 */
136#define SCL_CSEN BIT(0)
137#define SCL_WCAS_LAT(x) ((x) << 8)
138
139/* PHY SCL Latency */
140#define SCL_CAPCLKDLY(x) ((x) << 0)
141#define SCL_DDRCLKDLY(x) ((x) << 4)
142
143/* PHY SCL START */
144#define SCL_START BIT(28)
145#define SCL_EN BIT(26)
146#define SCL_LUBPASS (BIT(1) | BIT(0))
147
148#endif /* __MICROCHIP_DDR2_REGS_H */