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git01.mediatek.com / filogic / uboot / 3e174808f513e3e10f3e460c24677cbab5dfdd36 / . / arch / arm / cpu / armv7 / s5p-common / sromc.c
blob: 0fc170936ae442be71b7a7966ba4147af285e0db [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]2/*
3 * Copyright (C) 2010 Samsung Electronics
4 * Naveen Krishna Ch <ch.naveen@samsung.com>
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/io.h>
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]9#include <asm/arch/sromc.h>
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]10
11/*
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]12 * s5p_config_sromc() - select the proper SROMC Bank and configure the
13 * band width control and bank control registers
14 * srom_bank - SROM
15 * srom_bw_conf - SMC Band witdh reg configuration value
16 * srom_bc_conf - SMC Bank Control reg configuration value
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]17 */
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]18void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]19{
20 u32 tmp;
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]21 struct s5p_sromc *srom =
22 (struct s5p_sromc *)samsung_get_base_sromc();
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]23
24 /* Configure SMC_BW register to handle proper SROMC bank */
25 tmp = srom->bw;
26 tmp &= ~(0xF << (srom_bank * 4));
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]27 tmp |= srom_bw_conf;
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]28 srom->bw = tmp;
29
30 /* Configure SMC_BC register */
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]31 srom->bc[srom_bank] = srom_bc_conf;
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]32}