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git01.mediatek.com / filogic / uboot / 3e06eb341ebfef167ce039e66cfd14b06d469473 / . / board / ronetix / imx7-cm / spl.c
blob: d36f734e49cdda356db76b1affd966721820274f [file] [log] [blame]
Ilko Ilieve2480f12021-04-16 15:48:13 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2021 Ronetix GmbH
4 *
5 * Author: Ilko Iliev <iliev@ronetix.at>
6 */
7
8#include <common.h>
9#include <cpu_func.h>
10#include <init.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/mx7-pins.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/arch-mx7/mx7-ddr.h>
17#include <asm/mach-imx/iomux-v3.h>
18#include <asm/gpio.h>
19#include <fsl_esdhc_imx.h>
20#include <spl.h>
21
22static struct ddrc ddrc_regs_val = {
23 .mstr = 0x01040001,
24 .rfshtmg = 0x00400046,
25 .init1 = 0x00690000,
26 .init0 = 0x00020083,
27 .init3 = 0x09300004,
28 .init4 = 0x04080000,
29 .init5 = 0x00100004,
30 .rankctl = 0x0000033F,
31 .dramtmg0 = 0x09081109,
32 .dramtmg1 = 0x0007020d,
33 .dramtmg2 = 0x03040407,
34 .dramtmg3 = 0x00002006,
35 .dramtmg4 = 0x04020205,
36 .dramtmg5 = 0x03030202,
37 .dramtmg8 = 0x00000803,
38 .zqctl0 = 0x00800020,
39 .dfitmg0 = 0x02098204,
40 .dfitmg1 = 0x00030303,
41 .dfiupd0 = 0x80400003,
42 .dfiupd1 = 0x00100020,
43 .dfiupd2 = 0x80100004,
44 .addrmap4 = 0x00000F0F,
45 .odtcfg = 0x06000604,
46 .odtmap = 0x00000001,
47 .rfshtmg = 0x00400046,
48 .dramtmg0 = 0x09081109,
49 .addrmap0 = 0x0000001f,
50 .addrmap1 = 0x00080808,
51 .addrmap4 = 0x00000f0f,
52 .addrmap5 = 0x07070707,
53 .addrmap6 = 0x0f0f0707,
54};
55
56static struct ddrc_mp ddrc_mp_val = {
57 .pctrl_0 = 0x00000001,
58};
59
60static struct ddr_phy ddr_phy_regs_val = {
61 .phy_con0 = 0x17420f40,
62 .phy_con1 = 0x10210100,
63 .phy_con4 = 0x00060807,
64 .mdll_con0 = 0x1010007e,
65 .drvds_con0 = 0x00000d6e,
66 .cmd_sdll_con0 = 0x00000010,
67 .offset_lp_con0 = 0x0000000f,
68 .offset_rd_con0 = 0x0a0a0a0a,
69 .offset_wr_con0 = 0x06060606,
70};
71
72static struct mx7_calibration calib_param = {
73 .num_val = 5,
74 .values = {
75 0x0E407304,
76 0x0E447304,
77 0x0E447306,
78 0x0E447304,
79 0x0E447304,
80 },
81};
82
83static void ddr_init(void)
84{
85 mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param);
86}
87
88#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
89 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
90
91static iomux_v3_cfg_t const uart1_pads[] = {
92 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
93 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
94};
95
96void uart1_pads_set(void)
97{
98 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
99}
100
101void board_init_f(ulong dummy)
102{
103 arch_cpu_init();
104
105 uart1_pads_set();
106
107 timer_init();
108
109 preloader_console_init();
110
111 ddr_init();
112
113 memset(__bss_start, 0, __bss_end - __bss_start);
114
115 board_init_r(NULL, 0);
116}
117
118void reset_cpu(void)
119{
120}
121
122#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
123 PAD_CTL_HYS | PAD_CTL_PUE | \
124 PAD_CTL_PUS_PU47KOHM)
125
126static iomux_v3_cfg_t const usdhc1_pads[] = {
127 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133
134 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135};
136
137void usdhc1_pads_set(void)
138{
139 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
140}
141
142static struct fsl_esdhc_cfg usdhc_cfg = {
143 USDHC1_BASE_ADDR, 0, 4
144};
145
146int board_mmc_init(struct bd_info *bis)
147{
148 usdhc1_pads_set();
149 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
150 return fsl_esdhc_initialize(bis, &usdhc_cfg);
151}
152
153int board_mmc_getcd(struct mmc *mmc)
154{
155 return 1;
156}