| Ioana Ciornei | 606f140 | 2020-04-27 15:21:14 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7 |
| 4 | * |
| 5 | * Some assumptions are made: |
| 6 | * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6) |
| 7 | * * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10) |
| 8 | * |
| 9 | * Copyright 2020 NXP |
| 10 | * |
| 11 | */ |
| 12 | #include "fsl-lx2160a-qds.dtsi" |
| 13 | |
| 14 | &dpmac3 { |
| 15 | status = "okay"; |
| 16 | phy-handle = <&aquantia_phy1>; |
| 17 | phy-connection-type = "usxgmii"; |
| 18 | }; |
| 19 | |
| 20 | &dpmac4 { |
| 21 | status = "okay"; |
| 22 | phy-handle = <&aquantia_phy2>; |
| 23 | phy-connection-type = "usxgmii"; |
| 24 | }; |
| 25 | |
| 26 | &dpmac5 { |
| 27 | status = "okay"; |
| 28 | phy-handle = <&aquantia_phy3>; |
| 29 | phy-connection-type = "usxgmii"; |
| 30 | }; |
| 31 | |
| 32 | &dpmac6 { |
| 33 | status = "okay"; |
| 34 | phy-handle = <&aquantia_phy4>; |
| 35 | phy-connection-type = "usxgmii"; |
| 36 | }; |
| 37 | |
| 38 | &dpmac7 { |
| 39 | status = "okay"; |
| 40 | phy-handle = <&sgmii_phy1>; |
| 41 | phy-connection-type = "sgmii"; |
| 42 | }; |
| 43 | |
| 44 | &dpmac8 { |
| 45 | status = "okay"; |
| 46 | phy-handle = <&sgmii_phy2>; |
| 47 | phy-connection-type = "sgmii"; |
| 48 | }; |
| 49 | |
| 50 | &dpmac9 { |
| 51 | status = "okay"; |
| 52 | phy-handle = <&sgmii_phy3>; |
| 53 | phy-connection-type = "sgmii"; |
| 54 | }; |
| 55 | |
| 56 | &dpmac10 { |
| 57 | status = "okay"; |
| 58 | phy-handle = <&sgmii_phy4>; |
| 59 | phy-connection-type = "sgmii"; |
| 60 | }; |
| 61 | |
| 62 | &emdio1_slot1 { |
| 63 | aquantia_phy1: ethernet-phy@4 { |
| 64 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 65 | reg = <0x0>; |
| 66 | }; |
| 67 | |
| 68 | aquantia_phy2: ethernet-phy@5 { |
| 69 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 70 | reg = <0x1>; |
| 71 | }; |
| 72 | |
| 73 | aquantia_phy3: ethernet-phy@6 { |
| 74 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 75 | reg = <0x2>; |
| 76 | }; |
| 77 | |
| 78 | aquantia_phy4: ethernet-phy@7 { |
| 79 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 80 | reg = <0x3>; |
| 81 | }; |
| 82 | }; |
| 83 | |
| 84 | &emdio1_slot2 { |
| 85 | sgmii_phy1: ethernet-phy@1c { |
| 86 | reg = <0x1c>; |
| 87 | }; |
| 88 | |
| 89 | sgmii_phy2: ethernet-phy@1d { |
| 90 | reg = <0x1d>; |
| 91 | }; |
| 92 | |
| 93 | sgmii_phy3: ethernet-phy@1e { |
| 94 | reg = <0x1e>; |
| 95 | }; |
| 96 | |
| 97 | sgmii_phy4: ethernet-phy@1f { |
| 98 | reg = <0x1f>; |
| 99 | }; |
| 100 | }; |