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git01.mediatek.com / filogic / uboot / 3ddce57c228dc3408fce154757450545f0c532f7 / . / include / configs / t3corp.h
blob: 39ca7930baf81d537fe00ca5ed58c886ccd594e5 [file] [log] [blame]
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]1/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/*
22 * t3corp.h - configuration for T3CORP (460GT)
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 */
30#define CONFIG_460GT 1 /* Specific PPC460GT */
31#define CONFIG_440 1
32#define CONFIG_4xx 1 /* ... PPC4xx family */
33
34#define CONFIG_HOSTNAME t3corp
35
36/*
37 * Include common defines/options for all AMCC/APM eval boards
38 */
39#include "amcc-common.h"
40
41#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
42
43#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
44#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
45#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
46#define CONFIG_BOARD_TYPES 1 /* support board types */
47#define CONFIG_FIT
48#define CFG_ALT_MEMTEST
49
50/*
51 * Base addresses -- Note these are effective addresses where the
52 * actual resources get mapped (not physical addresses)
53 */
54#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
55#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
56#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
57
58#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe mem */
59#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe */
60#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
61
62#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
63#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
64#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
65#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
66
67#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit phys addr */
68
69/* base address of inbound PCIe window */
70#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit phys addr */
71
72/* EBC stuff */
73#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
74#define CONFIG_SYS_FLASH_SIZE (64 << 20)
75
76#define CONFIG_SYS_FPGA1_BASE 0xe0000000
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]77#define CONFIG_SYS_FPGA2_BASE 0xe2000000
78#define CONFIG_SYS_FPGA3_BASE 0xe4000000
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]79
80#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
81#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
82#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
83#define CONFIG_SYS_FLASH_BASE_PHYS \
84 (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
85 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
86
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]87#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]88#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
Wolfgang Denk2fc54d92010-09-10 23:04:05 +0200[diff] [blame]89#define CONFIG_SYS_SRAM_SIZE (256 << 10)
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]90#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
91
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]92/*
93 * Initial RAM & stack pointer (placed in OCM)
94 */
95#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
96#define CONFIG_SYS_INIT_RAM_END (4 << 10)
97#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
98#define CONFIG_SYS_GBL_DATA_OFFSET \
99 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
100#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
101
102/*
103 * Serial Port
104 */
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame^]105#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]106
107/*
108 * Environment
109 */
110/*
111 * Define here the location of the environment variables (flash).
112 */
113#define CONFIG_ENV_IS_IN_FLASH /* use flash for environment vars */
114
115/*
116 * Flash related
117 */
118#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
119#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
120#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]121#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]122
123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
124#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
125#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
126
127#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
128#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms*/
129
130#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buff'd writes (20x faster)*/
131#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
132
133#define CONFIG_ENV_SECT_SIZE 0x20000 /* sector size */
134#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - \
135 CONFIG_ENV_SECT_SIZE)
136#define CONFIG_ENV_SIZE 0x4000 /* env sector size */
137
138/* Address and size of Redundant Environment Sector */
139#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
140#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
141
142/*
143 * DDR2 SDRAM
144 */
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]145#define CONFIG_SYS_MBYTES_SDRAM 256
146#define CONFIG_DDR_ECC
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]147#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
148#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
149#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
150#undef CONFIG_PPC4xx_DDR_METHOD_A
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]151#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]152
153/* DDR1/2 SDRAM Device Control Register Data Values */
154/* Memory Queue */
155#define CONFIG_SYS_SDRAM_R0BAS (SDRAM_RXBAS_SDBA_ENCODE(0) | \
156 SDRAM_RXBAS_SDSZ_256)
157#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
158#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
159#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
160#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
161#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
162#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
163#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
164#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
165
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]166#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
167
168/* DDR1/2 SDRAM Device Control Register Data Values */
169#define CONFIG_SYS_SDRAM0_MB0CF (SDRAM_RXBAS_SDAM_MODE7 | \
170 SDRAM_RXBAS_SDBE_ENABLE)
171#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
172#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
173#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
174#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_MCHK_GEN | \
175 SDRAM_MCOPT1_PMU_OPEN | \
176 SDRAM_MCOPT1_DMWD_32 | \
177 SDRAM_MCOPT1_8_BANKS | \
178 SDRAM_MCOPT1_DDR2_TYPE | \
179 SDRAM_MCOPT1_QDEP | \
180 SDRAM_MCOPT1_RWOO_DISABLED | \
181 SDRAM_MCOPT1_WOOO_DISABLED | \
182 SDRAM_MCOPT1_DREF_NORMAL)
183#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
184#define CONFIG_SYS_SDRAM0_MODT0 SDRAM_MODT_EB0W_ENABLE
185#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
186#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
187#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
188#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
189 SDRAM_CODT_DQS_1_8_V_DDR2 | \
190 SDRAM_CODT_IO_NMODE)
191#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
192#define CONFIG_SYS_SDRAM0_INITPLR0 \
193 (SDRAM_INITPLR_ENABLE | \
194 SDRAM_INITPLR_IMWT_ENCODE(80) | \
195 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
196#define CONFIG_SYS_SDRAM0_INITPLR1 \
197 (SDRAM_INITPLR_ENABLE | \
198 SDRAM_INITPLR_IMWT_ENCODE(3) | \
199 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
200 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
201 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
202#define CONFIG_SYS_SDRAM0_INITPLR2 \
203 (SDRAM_INITPLR_ENABLE | \
204 SDRAM_INITPLR_IMWT_ENCODE(2) | \
205 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
206 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
207 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
208#define CONFIG_SYS_SDRAM0_INITPLR3 \
209 (SDRAM_INITPLR_ENABLE | \
210 SDRAM_INITPLR_IMWT_ENCODE(2) | \
211 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
212 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
213 SDRAM_INITPLR_IMA_ENCODE(0))
214#define CONFIG_SYS_SDRAM0_INITPLR4 \
215 (SDRAM_INITPLR_ENABLE | \
216 SDRAM_INITPLR_IMWT_ENCODE(2) | \
217 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
218 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
219 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE | \
220 JEDEC_MA_EMR_RTT_150OHM))
221#define CONFIG_SYS_SDRAM0_INITPLR5 \
222 (SDRAM_INITPLR_ENABLE | \
223 SDRAM_INITPLR_IMWT_ENCODE(200) | \
224 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
225 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
226 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
227 CAS_LATENCY | \
228 JEDEC_MA_MR_BLEN_4 | \
229 JEDEC_MA_MR_DLL_RESET))
230#define CONFIG_SYS_SDRAM0_INITPLR6 \
231 (SDRAM_INITPLR_ENABLE | \
232 SDRAM_INITPLR_IMWT_ENCODE(3) | \
233 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
234 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
235 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
236#define CONFIG_SYS_SDRAM0_INITPLR7 \
237 (SDRAM_INITPLR_ENABLE | \
238 SDRAM_INITPLR_IMWT_ENCODE(26) | \
239 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
240#define CONFIG_SYS_SDRAM0_INITPLR8 \
241 (SDRAM_INITPLR_ENABLE | \
242 SDRAM_INITPLR_IMWT_ENCODE(26) | \
243 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
244#define CONFIG_SYS_SDRAM0_INITPLR9 \
245 (SDRAM_INITPLR_ENABLE | \
246 SDRAM_INITPLR_IMWT_ENCODE(26) | \
247 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
248#define CONFIG_SYS_SDRAM0_INITPLR10 \
249 (SDRAM_INITPLR_ENABLE | \
250 SDRAM_INITPLR_IMWT_ENCODE(26) | \
251 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
252#define CONFIG_SYS_SDRAM0_INITPLR11 \
253 (SDRAM_INITPLR_ENABLE | \
254 SDRAM_INITPLR_IMWT_ENCODE(2) | \
255 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
256 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
257 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
258 CAS_LATENCY | \
259 JEDEC_MA_MR_BLEN_4))
260#define CONFIG_SYS_SDRAM0_INITPLR12 \
261 (SDRAM_INITPLR_ENABLE | \
262 SDRAM_INITPLR_IMWT_ENCODE(2) | \
263 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
264 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
265 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
266 JEDEC_MA_EMR_RDQS_DISABLE | \
267 JEDEC_MA_EMR_DQS_ENABLE | \
268 JEDEC_MA_EMR_RTT_150OHM | \
269 JEDEC_MA_EMR_ODS_NORMAL))
270#define CONFIG_SYS_SDRAM0_INITPLR13 \
271 (SDRAM_INITPLR_ENABLE | \
272 SDRAM_INITPLR_IMWT_ENCODE(2) | \
273 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
274 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
275 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
276 JEDEC_MA_EMR_RDQS_DISABLE | \
277 JEDEC_MA_EMR_DQS_ENABLE | \
278 JEDEC_MA_EMR_RTT_150OHM | \
279 JEDEC_MA_EMR_ODS_NORMAL))
280#define CONFIG_SYS_SDRAM0_INITPLR14 SDRAM_INITPLR_DISABLE
281#define CONFIG_SYS_SDRAM0_INITPLR15 SDRAM_INITPLR_DISABLE
282#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
283 SDRAM_RQDC_RQFD_ENCODE(56))
284#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(599)
285#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
286#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
287 SDRAM_DLCR_DLCS_CONT_DONE | \
288 SDRAM_DLCR_DLCV_ENCODE(155))
289#define CONFIG_SYS_SDRAM0_CLKTR SDRAM_CLKTR_CLKP_90_DEG_ADV
290#define CONFIG_SYS_SDRAM0_WRDTR SDRAM_WRDTR_WTR_90_DEG_ADV
291#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
292 SDRAM_SDTR1_RTW_2_CLK | \
293 SDRAM_SDTR1_RTRO_1_CLK)
294#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
295 SDRAM_SDTR2_WTR_2_CLK | \
296 SDRAM_SDTR2_XSNR_32_CLK | \
297 SDRAM_SDTR2_WPC_4_CLK | \
298 SDRAM_SDTR2_RPC_2_CLK | \
299 SDRAM_SDTR2_RP_3_CLK | \
300 SDRAM_SDTR2_RRD_2_CLK)
301#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
302 SDRAM_SDTR3_RC_ENCODE(11) | \
303 SDRAM_SDTR3_XCS | \
304 SDRAM_SDTR3_RFC_ENCODE(26))
305#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
306 CAS_LATENCY | \
307 SDRAM_MMODE_BLEN_4)
308#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_ENABLE | \
309 SDRAM_MEMODE_RTT_150OHM)
310
311/*
312 * I2C
313 */
314#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
315
316#define CONFIG_SYS_I2C_MULTI_EEPROMS
317#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
318#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
319#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
320#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
321
322/* I2C bootstrap EEPROM */
323#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
324#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
325#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
326
327/*
328 * Ethernet
329 */
330#define CONFIG_IBM_EMAC4_V4 1
331
332#define CONFIG_HAS_ETH0
333
334#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
335#define CONFIG_M88E1111_PHY
336/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
337#define CONFIG_M88E1111_DISABLE_FIBER
338
339#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
340#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
341#define CONFIG_PHY_DYNAMIC_ANEG 1
342
343/*
344 * Default environment variables
345 */
346#define CONFIG_EXTRA_ENV_SETTINGS \
347 CONFIG_AMCC_DEF_ENV \
348 CONFIG_AMCC_DEF_ENV_POWERPC \
349 CONFIG_AMCC_DEF_ENV_NOR_UPD \
350 "kernel_addr=fc000000\0" \
351 "fdt_addr=fc1e0000\0" \
352 "ramdisk_addr=fc200000\0" \
353 "pciconfighost=1\0" \
354 "pcie_mode=RP:RP\0" \
355 ""
356
357/*
358 * Commands additional to the ones defined in amcc-common.h
359 */
360#define CONFIG_CMD_CHIP_CONFIG
Stefan Roeseb3381f32010-07-22 19:06:27 +0200[diff] [blame]361#define CONFIG_CMD_ECCTEST
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]362#define CONFIG_CMD_PCI
363#define CONFIG_CMD_SDRAM
364
365/*
366 * PCI stuff
367 */
368/* General PCI */
369#define CONFIG_PCI /* include pci support */
370#define CONFIG_PCI_PNP /* do pci plug-and-play */
371#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
372#define CONFIG_PCI_CONFIG_HOST_BRIDGE
373
374/* Board-specific PCI, no PCI support, only PCIe */
375#undef CONFIG_SYS_PCI_TARGET_INIT
376#undef CONFIG_SYS_PCI_MASTER_INIT
377
378#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
379#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
380
381
382/*
383 * External Bus Controller (EBC) Setup
384 */
385
386/*
387 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
388 * boot EBC mapping only supports a maximum of 16MBytes
389 * (4.ff00.0000 - 4.ffff.ffff).
390 * To solve this problem, the flash has to get remapped to another
391 * EBC address which accepts bigger regions:
392 *
393 * 0xfc00.0000 -> 4.cc00.0000
394 */
395
396/* Memory Bank 0 (NOR-flash) */
397#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
398 EBC_BXAP_TWT_ENCODE(16) | \
399 EBC_BXAP_BCE_DISABLE | \
400 EBC_BXAP_BCT_2TRANS | \
401 EBC_BXAP_CSN_ENCODE(1) | \
402 EBC_BXAP_OEN_ENCODE(1) | \
403 EBC_BXAP_WBN_ENCODE(1) | \
404 EBC_BXAP_WBF_ENCODE(1) | \
405 EBC_BXAP_TH_ENCODE(7) | \
406 EBC_BXAP_RE_DISABLED | \
407 EBC_BXAP_SOR_DELAYED | \
408 EBC_BXAP_BEM_WRITEONLY | \
409 EBC_BXAP_PEN_DISABLED)
410#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
411 EBC_BXCR_BS_16MB | \
412 EBC_BXCR_BU_RW | \
413 EBC_BXCR_BW_16BIT)
414
415/* Memory Bank 1 (FPGA 1) */
416#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
417 EBC_BXAP_TWT_ENCODE(5) | \
418 EBC_BXAP_CSN_ENCODE(0) | \
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]419 EBC_BXAP_OEN_ENCODE(3) | \
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]420 EBC_BXAP_WBN_ENCODE(0) | \
421 EBC_BXAP_WBF_ENCODE(0) | \
422 EBC_BXAP_TH_ENCODE(1) | \
423 EBC_BXAP_RE_DISABLED | \
424 EBC_BXAP_SOR_DELAYED | \
425 EBC_BXAP_BEM_RW | \
426 EBC_BXAP_PEN_DISABLED)
427#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]428 EBC_BXCR_BS_32MB | \
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]429 EBC_BXCR_BU_RW | \
430 EBC_BXCR_BW_32BIT)
431
432/* Memory Bank 2 (FPGA 2) */
433#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
434 EBC_BXAP_TWT_ENCODE(5) | \
435 EBC_BXAP_CSN_ENCODE(0) | \
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]436 EBC_BXAP_OEN_ENCODE(3) | \
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]437 EBC_BXAP_WBN_ENCODE(0) | \
438 EBC_BXAP_WBF_ENCODE(0) | \
439 EBC_BXAP_TH_ENCODE(1) | \
440 EBC_BXAP_RE_DISABLED | \
441 EBC_BXAP_SOR_DELAYED | \
442 EBC_BXAP_BEM_RW | \
443 EBC_BXAP_PEN_DISABLED)
444#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]445 EBC_BXCR_BS_16MB | \
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]446 EBC_BXCR_BU_RW | \
447 EBC_BXCR_BW_32BIT)
448
449/* Memory Bank 3 (FPGA 3) */
450#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
451 EBC_BXAP_TWT_ENCODE(5) | \
452 EBC_BXAP_CSN_ENCODE(0) | \
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]453 EBC_BXAP_OEN_ENCODE(3) | \
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]454 EBC_BXAP_WBN_ENCODE(0) | \
455 EBC_BXAP_WBF_ENCODE(0) | \
456 EBC_BXAP_TH_ENCODE(1) | \
457 EBC_BXAP_RE_DISABLED | \
458 EBC_BXAP_SOR_DELAYED | \
459 EBC_BXAP_BEM_RW | \
460 EBC_BXAP_PEN_DISABLED)
461#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
Stefan Roese45f78092010-07-19 14:24:22 +0200[diff] [blame]462 EBC_BXCR_BS_16MB | \
Stefan Roese34447422010-05-19 11:11:15 +0200[diff] [blame]463 EBC_BXCR_BU_RW | \
464 EBC_BXCR_BW_32BIT)
465
466/*
467 * PPC4xx GPIO Configuration
468 */
469
470#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
471{ \
472/* GPIO Core 0 */ \
473{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
474{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
475{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
476{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
477{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
478{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
479{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
480{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
481{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
482{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
483{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
484{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
485{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
486{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
487{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
488{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
489{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
490{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
491{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
492{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
493{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
494{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
495{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
496{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
497{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
498{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
499{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
500{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
501{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
502{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
503{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
504{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
505}, \
506{ \
507/* GPIO Core 1 */ \
508{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
509{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
510{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
511{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
512{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
513{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
514{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
515{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
516{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
517{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
518{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
519{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
520{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
521{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
522{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
523{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
524{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
525{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
526{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
527{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
528{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
529{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
530{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
531{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
532{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
533{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
534{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
535{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
536{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
537{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
538{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
540} \
541}
542
543#endif /* __CONFIG_H */