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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Vanessa Maegima27142c32017-05-08 13:17:28 -03002/*
3 * Copyright (C) 2017 NXP Semiconductors
4 *
5 * Configuration settings for the i.MX7D Pico board.
Vanessa Maegima27142c32017-05-08 13:17:28 -03006 */
7
8#ifndef __PICO_IMX7D_CONFIG_H
9#define __PICO_IMX7D_CONFIG_H
10
11#include "mx7_common.h"
12
13#define PHYS_SDRAM_SIZE SZ_1G
14
15/* Size of malloc() pool */
16#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
17
18#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
19
20/* Network */
21#define CONFIG_FEC_MXC
22#define CONFIG_MII
23#define CONFIG_FEC_XCV_TYPE RGMII
24#define CONFIG_ETHPRIME "FEC"
25#define CONFIG_FEC_MXC_PHYADDR 1
26
Vanessa Maegima27142c32017-05-08 13:17:28 -030027#define CONFIG_PHY_ATHEROS
28
29/* ENET1 */
30#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
31
32/* MMC Config */
33#define CONFIG_SYS_FSL_ESDHC_ADDR 0
34
35#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
36#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
37
38#define CONFIG_EXTRA_ENV_SETTINGS \
39 "script=boot.scr\0" \
40 "image=zImage\0" \
41 "console=ttymxc4\0" \
42 "fdt_high=0xffffffff\0" \
43 "initrd_high=0xffffffff\0" \
Fabio Estevam821f6a62018-06-29 15:19:06 -030044 "fdtfile=imx7d-pico-pi.dtb\0" \
Vanessa Maegima27142c32017-05-08 13:17:28 -030045 "fdt_addr=0x83000000\0" \
Fabio Estevam821f6a62018-06-29 15:19:06 -030046 "fdt_addr_r=0x83000000\0" \
47 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
48 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
49 "ramdisk_addr_r=0x83000000\0" \
50 "ramdiskaddr=0x83000000\0" \
51 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
Otavio Salvador3dc4bc52018-06-29 15:19:07 -030052 "finduuid=part uuid mmc 0:1 uuid\0" \
Fabio Estevam821f6a62018-06-29 15:19:06 -030053 BOOTENV
54
55#define BOOT_TARGET_DEVICES(func) \
56 func(MMC, mmc, 0) \
57 func(DHCP, dhcp, na)
Vanessa Maegima27142c32017-05-08 13:17:28 -030058
Fabio Estevam821f6a62018-06-29 15:19:06 -030059#include <config_distro_bootcmd.h>
Vanessa Maegima27142c32017-05-08 13:17:28 -030060
61#define CONFIG_SYS_MEMTEST_START 0x80000000
62#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
63
64#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
65#define CONFIG_SYS_HZ 1000
66
67/* Physical Memory Map */
68#define CONFIG_NR_DRAM_BANKS 1
69#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
70
71#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
72#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
73#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
74
75#define CONFIG_SYS_INIT_SP_OFFSET \
76 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
77#define CONFIG_SYS_INIT_SP_ADDR \
78 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
79
80/* I2C configs */
81#define CONFIG_SYS_I2C
82#define CONFIG_SYS_I2C_MXC
83#define CONFIG_SYS_I2C_MXC_I2C1
84#define CONFIG_SYS_I2C_MXC_I2C2
85#define CONFIG_SYS_I2C_MXC_I2C3
86#define CONFIG_SYS_I2C_MXC_I2C4
87#define CONFIG_SYS_I2C_SPEED 100000
88
89/* PMIC */
90#define CONFIG_POWER
91#define CONFIG_POWER_I2C
92#define CONFIG_POWER_PFUZE3000
93#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
94
95/* FLASH and environment organization */
96#define CONFIG_ENV_SIZE SZ_8K
Vanessa Maegima27142c32017-05-08 13:17:28 -030097
98#define CONFIG_ENV_OFFSET (8 * SZ_64K)
99#define CONFIG_SYS_FSL_USDHC_NUM 2
100
101#define CONFIG_SYS_MMC_ENV_DEV 0
102#define CONFIG_SYS_MMC_ENV_PART 0
103
104/* USB Configs */
105#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
106#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
107#define CONFIG_MXC_USB_FLAGS 0
108#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
109
110#define CONFIG_IMX_THERMAL
111
Vanessa Maegima27142c32017-05-08 13:17:28 -0300112#endif