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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk5b845b62002-08-21 21:57:24 +00002/*
wdenk9b7f3842003-10-09 20:09:04 +00003 * (C) Copyright 2003
4 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
5 *
wdenk5b845b62002-08-21 21:57:24 +00006 * (C) Copyright 2002
7 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk5b845b62002-08-21 21:57:24 +00008 */
9
10/*
wdenk5b845b62002-08-21 21:57:24 +000011 * Altera FPGA support
12 */
13#include <common.h>
Marek Vasutb9d4df32014-09-16 20:33:54 +020014#include <errno.h>
wdenk9b7f3842003-10-09 20:09:04 +000015#include <ACEX1K.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
eran liberty4c373a92008-03-27 00:50:49 +010017#include <stratixII.h>
wdenk5b845b62002-08-21 21:57:24 +000018
Marek Vasut9e3a8442014-09-16 20:21:42 +020019/* Define FPGA_DEBUG to 1 to get debug printf's */
20#define FPGA_DEBUG 0
wdenk5b845b62002-08-21 21:57:24 +000021
Marek Vasutf5d25e42014-09-16 21:17:51 +020022static const struct altera_fpga {
23 enum altera_family family;
24 const char *name;
25 int (*load)(Altera_desc *, const void *, size_t);
26 int (*dump)(Altera_desc *, const void *, size_t);
27 int (*info)(Altera_desc *);
28} altera_fpga[] = {
29#if defined(CONFIG_FPGA_ACEX1K)
30 { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
31 { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
32#elif defined(CONFIG_FPGA_CYCLON2)
33 { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
34 { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
35#endif
36#if defined(CONFIG_FPGA_STRATIX_II)
37 { Altera_StratixII, "StratixII", StratixII_load,
38 StratixII_dump, StratixII_info },
39#endif
Stefan Roesed919d722016-02-12 13:48:02 +010040#if defined(CONFIG_FPGA_STRATIX_V)
41 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
42#endif
Ang, Chee Hongff14f162018-12-19 18:35:15 -080043#if defined(CONFIG_FPGA_STRATIX10)
44 { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
45#endif
Pavel Machekc7213802014-09-08 14:08:45 +020046#if defined(CONFIG_FPGA_SOCFPGA)
47 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
48#endif
Marek Vasutf5d25e42014-09-16 21:17:51 +020049};
50
Marek Vasutff4072c2014-09-16 20:32:51 +020051static int altera_validate(Altera_desc *desc, const char *fn)
52{
53 if (!desc) {
54 printf("%s: NULL descriptor!\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020055 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020056 }
57
58 if ((desc->family < min_altera_type) ||
59 (desc->family > max_altera_type)) {
60 printf("%s: Invalid family type, %d\n", fn, desc->family);
Marek Vasutb9d4df32014-09-16 20:33:54 +020061 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020062 }
63
64 if ((desc->iface < min_altera_iface_type) ||
65 (desc->iface > max_altera_iface_type)) {
66 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
Marek Vasutb9d4df32014-09-16 20:33:54 +020067 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020068 }
69
70 if (!desc->size) {
71 printf("%s: NULL part size\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020072 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020073 }
74
Marek Vasutb9d4df32014-09-16 20:33:54 +020075 return 0;
Marek Vasutff4072c2014-09-16 20:32:51 +020076}
wdenk9b7f3842003-10-09 20:09:04 +000077
Marek Vasutf5d25e42014-09-16 21:17:51 +020078static const struct altera_fpga *
79altera_desc_to_fpga(Altera_desc *desc, const char *fn)
wdenk5b845b62002-08-21 21:57:24 +000080{
Marek Vasutf5d25e42014-09-16 21:17:51 +020081 int i;
wdenk9b7f3842003-10-09 20:09:04 +000082
Marek Vasutf5d25e42014-09-16 21:17:51 +020083 if (altera_validate(desc, fn)) {
84 printf("%s: Invalid device descriptor\n", fn);
85 return NULL;
Marek Vasut18221352014-09-16 20:29:24 +020086 }
87
Marek Vasutf5d25e42014-09-16 21:17:51 +020088 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
89 if (desc->family == altera_fpga[i].family)
90 break;
91 }
wdenk9b7f3842003-10-09 20:09:04 +000092
Marek Vasutf5d25e42014-09-16 21:17:51 +020093 if (i == ARRAY_SIZE(altera_fpga)) {
94 printf("%s: Unsupported family type, %d\n", fn, desc->family);
95 return NULL;
wdenk9b7f3842003-10-09 20:09:04 +000096 }
97
Marek Vasutf5d25e42014-09-16 21:17:51 +020098 return &altera_fpga[i];
wdenk5b845b62002-08-21 21:57:24 +000099}
100
Marek Vasutf5d25e42014-09-16 21:17:51 +0200101int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +0000102{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200103 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000104
Marek Vasutf5d25e42014-09-16 21:17:51 +0200105 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200106 return FPGA_FAIL;
Marek Vasut18221352014-09-16 20:29:24 +0200107
Marek Vasutf5d25e42014-09-16 21:17:51 +0200108 debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
109 __func__, fpga->name);
110 if (fpga->load)
111 return fpga->load(desc, buf, bsize);
112 return 0;
113}
wdenk9b7f3842003-10-09 20:09:04 +0000114
Marek Vasutf5d25e42014-09-16 21:17:51 +0200115int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
116{
117 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000118
Marek Vasutf5d25e42014-09-16 21:17:51 +0200119 if (!fpga)
120 return FPGA_FAIL;
121
122 debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
123 __func__, fpga->name);
124 if (fpga->dump)
125 return fpga->dump(desc, buf, bsize);
126 return 0;
wdenk5b845b62002-08-21 21:57:24 +0000127}
128
Marek Vasut18221352014-09-16 20:29:24 +0200129int altera_info(Altera_desc *desc)
wdenk5b845b62002-08-21 21:57:24 +0000130{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200131 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000132
Marek Vasutf5d25e42014-09-16 21:17:51 +0200133 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200134 return FPGA_FAIL;
wdenk9b7f3842003-10-09 20:09:04 +0000135
Marek Vasutf5d25e42014-09-16 21:17:51 +0200136 printf("Family: \t%s\n", fpga->name);
wdenk9b7f3842003-10-09 20:09:04 +0000137
Marek Vasut18221352014-09-16 20:29:24 +0200138 printf("Interface type:\t");
139 switch (desc->iface) {
140 case passive_serial:
141 printf("Passive Serial (PS)\n");
142 break;
143 case passive_parallel_synchronous:
144 printf("Passive Parallel Synchronous (PPS)\n");
145 break;
146 case passive_parallel_asynchronous:
147 printf("Passive Parallel Asynchronous (PPA)\n");
148 break;
149 case passive_serial_asynchronous:
150 printf("Passive Serial Asynchronous (PSA)\n");
151 break;
152 case altera_jtag_mode: /* Not used */
153 printf("JTAG Mode\n");
154 break;
155 case fast_passive_parallel:
156 printf("Fast Passive Parallel (FPP)\n");
157 break;
158 case fast_passive_parallel_security:
159 printf("Fast Passive Parallel with Security (FPPS)\n");
160 break;
Ang, Chee Hongff14f162018-12-19 18:35:15 -0800161 case secure_device_manager_mailbox:
162 puts("Secure Device Manager (SDM) Mailbox\n");
163 break;
Marek Vasut18221352014-09-16 20:29:24 +0200164 /* Add new interface types here */
165 default:
166 printf("Unsupported interface type, %d\n", desc->iface);
167 }
168
169 printf("Device Size: \t%zd bytes\n"
170 "Cookie: \t0x%x (%d)\n",
171 desc->size, desc->cookie, desc->cookie);
wdenk9b7f3842003-10-09 20:09:04 +0000172
Marek Vasut18221352014-09-16 20:29:24 +0200173 if (desc->iface_fns) {
174 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
Marek Vasutf5d25e42014-09-16 21:17:51 +0200175 if (fpga->info)
176 fpga->info(desc);
wdenk9b7f3842003-10-09 20:09:04 +0000177 } else {
Marek Vasut18221352014-09-16 20:29:24 +0200178 printf("No Device Function Table.\n");
wdenk9b7f3842003-10-09 20:09:04 +0000179 }
180
Marek Vasutf5d25e42014-09-16 21:17:51 +0200181 return FPGA_SUCCESS;
wdenk9b7f3842003-10-09 20:09:04 +0000182}