Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 2 | /* |
| 3 | * WORK Microwave work_92105 board configuration file |
| 4 | * |
| 5 | * (C) Copyright 2014 DENX Software Engineering GmbH |
| 6 | * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_WORK_92105_H__ |
| 10 | #define __CONFIG_WORK_92105_H__ |
| 11 | |
| 12 | /* SoC and board defines */ |
| 13 | #include <linux/sizes.h> |
| 14 | #include <asm/arch/cpu.h> |
| 15 | |
| 16 | /* |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 17 | * Memory configurations |
| 18 | */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 19 | #define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE |
| 20 | #define CFG_SYS_SDRAM_SIZE SZ_128M |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 21 | |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 22 | /* |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 23 | * U-Boot General Configurations |
| 24 | */ |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 25 | |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 26 | /* |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 27 | * NAND chip timings for FIXME: which one? |
| 28 | */ |
| 29 | |
Tom Rini | 59cbfca | 2022-12-04 10:04:38 -0500 | [diff] [blame] | 30 | #define CFG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 |
Tom Rini | 326ca48 | 2022-12-04 10:04:34 -0500 | [diff] [blame] | 31 | #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 |
Tom Rini | ac8d571 | 2022-12-04 10:04:35 -0500 | [diff] [blame] | 32 | #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 |
Tom Rini | 2f54d77 | 2022-12-04 10:04:36 -0500 | [diff] [blame] | 33 | #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 |
Tom Rini | 045a295 | 2022-12-04 10:04:37 -0500 | [diff] [blame] | 34 | #define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 |
Tom Rini | d67a37f | 2022-12-04 10:04:39 -0500 | [diff] [blame] | 35 | #define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000 |
Tom Rini | 8678560 | 2022-12-04 10:04:40 -0500 | [diff] [blame] | 36 | #define CFG_LPC32XX_NAND_MLC_WR_LOW 83333333 |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 37 | |
| 38 | /* |
| 39 | * NAND |
| 40 | */ |
| 41 | |
| 42 | /* driver configuration */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 43 | #define CFG_SYS_MAX_NAND_CHIPS 1 |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 44 | #define CFG_SYS_NAND_BASE MLC_NAND_BASE |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 45 | |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 46 | /* |
| 47 | * GPIO |
| 48 | */ |
| 49 | |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 50 | /* |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 51 | * Environment |
| 52 | */ |
| 53 | |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 54 | /* |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 55 | * SPL |
| 56 | */ |
| 57 | |
| 58 | /* SPL will be executed at offset 0 */ |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 59 | /* SPL will use SRAM as stack */ |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 60 | /* Use the framework and generic lib */ |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 61 | /* SPL will use serial */ |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 62 | /* SPL will load U-Boot from NAND offset 0x40000 */ |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 63 | /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 64 | #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE |
| 65 | #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 66 | |
| 67 | /* |
| 68 | * Include SoC specific configuration |
| 69 | */ |
| 70 | #include <asm/arch/config.h> |
| 71 | |
| 72 | #endif /* __CONFIG_WORK_92105_H__*/ |