blob: 4a3ab6111276e6239baf61afd696d5f92a31d792 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotardf2505b12017-09-05 11:04:24 +02002/*
3 * STiH407 family DWC3 specific Glue layer
4 *
Patrice Chotard9e216242017-10-23 09:53:57 +02005 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
Patrice Chotard5d9950d2020-12-02 18:47:30 +01006 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotardf2505b12017-09-05 11:04:24 +02007 */
8
9#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Patrice Chotardf2505b12017-09-05 11:04:24 +020012#include <asm/io.h>
13#include <dm.h>
14#include <errno.h>
Patrice Chotardf2505b12017-09-05 11:04:24 +020015#include <dm/lists.h>
16#include <regmap.h>
17#include <reset-uclass.h>
18#include <syscon.h>
19#include <usb.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060020#include <linux/printk.h>
Patrice Chotardf2505b12017-09-05 11:04:24 +020021
22#include <linux/usb/dwc3.h>
23#include <linux/usb/otg.h>
24#include <dwc3-sti-glue.h>
25
26DECLARE_GLOBAL_DATA_PTR;
27
28/*
Simon Glassb75b15b2020-12-03 16:55:23 -070029 * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure
Patrice Chotardf2505b12017-09-05 11:04:24 +020030 * @syscfg_base: addr for the glue syscfg
31 * @glue_base: addr for the glue registers
32 * @syscfg_offset: usb syscfg control offset
33 * @powerdown_ctl: rest controller for powerdown signal
34 * @softreset_ctl: reset controller for softreset signal
35 * @mode: drd static host/device config
36 */
Simon Glassb75b15b2020-12-03 16:55:23 -070037struct sti_dwc3_glue_plat {
Patrice Chotardf2505b12017-09-05 11:04:24 +020038 phys_addr_t syscfg_base;
39 phys_addr_t glue_base;
40 phys_addr_t syscfg_offset;
41 struct reset_ctl powerdown_ctl;
42 struct reset_ctl softreset_ctl;
43 enum usb_dr_mode mode;
44};
45
Simon Glassb75b15b2020-12-03 16:55:23 -070046static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat)
Patrice Chotardf2505b12017-09-05 11:04:24 +020047{
48 unsigned long val;
49
50 val = readl(plat->syscfg_base + plat->syscfg_offset);
51
52 val &= USB3_CONTROL_MASK;
53
54 switch (plat->mode) {
55 case USB_DR_MODE_PERIPHERAL:
56 val &= ~(USB3_DELAY_VBUSVALID
57 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
58 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
59 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
60
61 val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
62 break;
63
64 case USB_DR_MODE_HOST:
65 val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
66 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
67 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
68 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
69
70 val |= USB3_DELAY_VBUSVALID;
71 break;
72
73 default:
Masahiro Yamada81e10422017-09-16 14:10:41 +090074 pr_err("Unsupported mode of operation %d\n", plat->mode);
Patrice Chotardf2505b12017-09-05 11:04:24 +020075 return -EINVAL;
76 }
77 writel(val, plat->syscfg_base + plat->syscfg_offset);
78
79 return 0;
80}
81
Simon Glassb75b15b2020-12-03 16:55:23 -070082static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat)
Patrice Chotardf2505b12017-09-05 11:04:24 +020083{
84 unsigned long reg;
85
86 reg = readl(plat->glue_base + CLKRST_CTRL);
87
88 reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
89 reg &= ~SW_PIPEW_RESET_N;
90
91 writel(reg, plat->glue_base + CLKRST_CTRL);
92
93 /* configure mux for vbus, powerpresent and bvalid signals */
94 reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
95
96 reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
97 SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
98 SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
99
100 writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
101
102 setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
103}
104
Simon Glassaad29ae2020-12-03 16:55:21 -0700105static int sti_dwc3_glue_of_to_plat(struct udevice *dev)
Patrice Chotardf2505b12017-09-05 11:04:24 +0200106{
Simon Glassb75b15b2020-12-03 16:55:23 -0700107 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200108 struct udevice *syscon;
109 struct regmap *regmap;
110 int ret;
111 u32 reg[4];
112
Simon Glassa7ece582020-12-19 10:40:14 -0700113 ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg,
114 ARRAY_SIZE(reg));
Patrice Chotardf2505b12017-09-05 11:04:24 +0200115 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900116 pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200117 return ret;
118 }
119
120 plat->glue_base = reg[0];
121 plat->syscfg_offset = reg[2];
122
123 /* get corresponding syscon phandle */
124 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg",
125 &syscon);
126 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900127 pr_err("unable to find syscon device (%d)\n", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200128 return ret;
129 }
130
131 /* get syscfg-reg base address */
132 regmap = syscon_get_regmap(syscon);
133 if (!regmap) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900134 pr_err("unable to find regmap\n");
Patrice Chotardf2505b12017-09-05 11:04:24 +0200135 return -ENODEV;
136 }
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +0900137 plat->syscfg_base = regmap->ranges[0].start;
Patrice Chotardf2505b12017-09-05 11:04:24 +0200138
139 /* get powerdown reset */
140 ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl);
141 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900142 pr_err("can't get powerdown reset for %s (%d)", dev->name, ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200143 return ret;
144 }
145
146 /* get softreset reset */
147 ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl);
148 if (ret)
Masahiro Yamada81e10422017-09-16 14:10:41 +0900149 pr_err("can't get soft reset for %s (%d)", dev->name, ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200150
151 return ret;
152};
153
154static int sti_dwc3_glue_bind(struct udevice *dev)
155{
Simon Glassb75b15b2020-12-03 16:55:23 -0700156 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Kever Yang1b807052020-03-04 08:59:50 +0800157 ofnode node, dwc3_node;
Patrice Chotardf2505b12017-09-05 11:04:24 +0200158
Kever Yang1b807052020-03-04 08:59:50 +0800159 /* Find snps,dwc3 node from subnode */
Simon Glassa7ece582020-12-19 10:40:14 -0700160 ofnode_for_each_subnode(node, dev_ofnode(dev)) {
Kever Yang1b807052020-03-04 08:59:50 +0800161 if (ofnode_device_is_compatible(node, "snps,dwc3"))
162 dwc3_node = node;
Patrice Chotardf2505b12017-09-05 11:04:24 +0200163 }
164
Patrice Chotard7c7640a2020-06-29 11:19:02 +0200165 if (!ofnode_valid(dwc3_node)) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900166 pr_err("Can't find dwc3 subnode for %s\n", dev->name);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200167 return -ENODEV;
168 }
169
170 /* retrieve the DWC3 dual role mode */
171 plat->mode = usb_get_dr_mode(dwc3_node);
172 if (plat->mode == USB_DR_MODE_UNKNOWN)
173 /* by default set dual role mode to HOST */
174 plat->mode = USB_DR_MODE_HOST;
175
176 return dm_scan_fdt_dev(dev);
177}
178
179static int sti_dwc3_glue_probe(struct udevice *dev)
180{
Simon Glassb75b15b2020-12-03 16:55:23 -0700181 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200182 int ret;
183
184 /* deassert both powerdown and softreset */
185 ret = reset_deassert(&plat->powerdown_ctl);
186 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900187 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200188 return ret;
189 }
190
191 ret = reset_deassert(&plat->softreset_ctl);
192 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900193 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200194 goto softreset_err;
195 }
196
197 ret = sti_dwc3_glue_drd_init(plat);
198 if (ret)
199 goto init_err;
200
201 sti_dwc3_glue_init(plat);
202
203 return 0;
204
205init_err:
206 ret = reset_assert(&plat->softreset_ctl);
207 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900208 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200209 return ret;
210 }
211
212softreset_err:
213 ret = reset_assert(&plat->powerdown_ctl);
214 if (ret < 0)
Masahiro Yamada81e10422017-09-16 14:10:41 +0900215 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200216
217 return ret;
218}
219
220static int sti_dwc3_glue_remove(struct udevice *dev)
221{
Simon Glassb75b15b2020-12-03 16:55:23 -0700222 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200223 int ret;
224
225 /* assert both powerdown and softreset */
226 ret = reset_assert(&plat->powerdown_ctl);
227 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900228 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200229 return ret;
230 }
231
232 ret = reset_assert(&plat->softreset_ctl);
233 if (ret < 0)
Masahiro Yamada81e10422017-09-16 14:10:41 +0900234 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200235
236 return ret;
237}
238
239static const struct udevice_id sti_dwc3_glue_ids[] = {
240 { .compatible = "st,stih407-dwc3" },
241 { }
242};
243
244U_BOOT_DRIVER(dwc3_sti_glue) = {
245 .name = "dwc3_sti_glue",
Patrice Chotard190ee832020-04-28 13:49:50 +0200246 .id = UCLASS_NOP,
Patrice Chotardf2505b12017-09-05 11:04:24 +0200247 .of_match = sti_dwc3_glue_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700248 .of_to_plat = sti_dwc3_glue_of_to_plat,
Patrice Chotardf2505b12017-09-05 11:04:24 +0200249 .probe = sti_dwc3_glue_probe,
250 .remove = sti_dwc3_glue_remove,
251 .bind = sti_dwc3_glue_bind,
Simon Glassb75b15b2020-12-03 16:55:23 -0700252 .plat_auto = sizeof(struct sti_dwc3_glue_plat),
Patrice Chotardf2505b12017-09-05 11:04:24 +0200253 .flags = DM_FLAG_ALLOC_PRIV_DMA,
254};