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git01.mediatek.com / filogic / uboot / 3d9a20dadd6c27db13cbde1cb543d3c3589fb983 / . / drivers / pinctrl / renesas / pfc-r8a77951.c
blob: 5d1c81c3eae5720596a635034e8d879bab2a86cd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3 * R8A77951 processor support - PFC hardware block.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <dm/pinctrl.h>
12#include <linux/kernel.h>
13
14#include "sh_pfc.h"
15
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]17
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]18#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]19 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]21 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]22 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]23 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]27 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]28 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]31
32#define CPU_ALL_NOGP(fn) \
33 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
53 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
72 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
73 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
74 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
76
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]77/*
78 * F_() : just information
79 * FM() : macro for FN_xxx / xxx_MARK
80 */
81
82/* GPSR0 */
83#define GPSR0_15 F_(D15, IP7_11_8)
84#define GPSR0_14 F_(D14, IP7_7_4)
85#define GPSR0_13 F_(D13, IP7_3_0)
86#define GPSR0_12 F_(D12, IP6_31_28)
87#define GPSR0_11 F_(D11, IP6_27_24)
88#define GPSR0_10 F_(D10, IP6_23_20)
89#define GPSR0_9 F_(D9, IP6_19_16)
90#define GPSR0_8 F_(D8, IP6_15_12)
91#define GPSR0_7 F_(D7, IP6_11_8)
92#define GPSR0_6 F_(D6, IP6_7_4)
93#define GPSR0_5 F_(D5, IP6_3_0)
94#define GPSR0_4 F_(D4, IP5_31_28)
95#define GPSR0_3 F_(D3, IP5_27_24)
96#define GPSR0_2 F_(D2, IP5_23_20)
97#define GPSR0_1 F_(D1, IP5_19_16)
98#define GPSR0_0 F_(D0, IP5_15_12)
99
100/* GPSR1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]101#define GPSR1_28 FM(CLKOUT)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]102#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
103#define GPSR1_26 F_(WE1_N, IP5_7_4)
104#define GPSR1_25 F_(WE0_N, IP5_3_0)
105#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
106#define GPSR1_23 F_(RD_N, IP4_27_24)
107#define GPSR1_22 F_(BS_N, IP4_23_20)
108#define GPSR1_21 F_(CS1_N, IP4_19_16)
109#define GPSR1_20 F_(CS0_N, IP4_15_12)
110#define GPSR1_19 F_(A19, IP4_11_8)
111#define GPSR1_18 F_(A18, IP4_7_4)
112#define GPSR1_17 F_(A17, IP4_3_0)
113#define GPSR1_16 F_(A16, IP3_31_28)
114#define GPSR1_15 F_(A15, IP3_27_24)
115#define GPSR1_14 F_(A14, IP3_23_20)
116#define GPSR1_13 F_(A13, IP3_19_16)
117#define GPSR1_12 F_(A12, IP3_15_12)
118#define GPSR1_11 F_(A11, IP3_11_8)
119#define GPSR1_10 F_(A10, IP3_7_4)
120#define GPSR1_9 F_(A9, IP3_3_0)
121#define GPSR1_8 F_(A8, IP2_31_28)
122#define GPSR1_7 F_(A7, IP2_27_24)
123#define GPSR1_6 F_(A6, IP2_23_20)
124#define GPSR1_5 F_(A5, IP2_19_16)
125#define GPSR1_4 F_(A4, IP2_15_12)
126#define GPSR1_3 F_(A3, IP2_11_8)
127#define GPSR1_2 F_(A2, IP2_7_4)
128#define GPSR1_1 F_(A1, IP2_3_0)
129#define GPSR1_0 F_(A0, IP1_31_28)
130
131/* GPSR2 */
132#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
133#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
134#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
135#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
136#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
137#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
138#define GPSR2_8 F_(PWM2_A, IP1_27_24)
139#define GPSR2_7 F_(PWM1_A, IP1_23_20)
140#define GPSR2_6 F_(PWM0, IP1_19_16)
141#define GPSR2_5 F_(IRQ5, IP1_15_12)
142#define GPSR2_4 F_(IRQ4, IP1_11_8)
143#define GPSR2_3 F_(IRQ3, IP1_7_4)
144#define GPSR2_2 F_(IRQ2, IP1_3_0)
145#define GPSR2_1 F_(IRQ1, IP0_31_28)
146#define GPSR2_0 F_(IRQ0, IP0_27_24)
147
148/* GPSR3 */
149#define GPSR3_15 F_(SD1_WP, IP11_23_20)
150#define GPSR3_14 F_(SD1_CD, IP11_19_16)
151#define GPSR3_13 F_(SD0_WP, IP11_15_12)
152#define GPSR3_12 F_(SD0_CD, IP11_11_8)
153#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
154#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
155#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
156#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
157#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
158#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
159#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
160#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
161#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
162#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
163#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
164#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
165
166/* GPSR4 */
167#define GPSR4_17 F_(SD3_DS, IP11_7_4)
168#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
169#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
170#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
171#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
172#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
173#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
174#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
175#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
176#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
177#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
178#define GPSR4_6 F_(SD2_DS, IP9_27_24)
179#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
180#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
181#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
182#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
183#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
184#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
185
186/* GPSR5 */
187#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
188#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
189#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
190#define GPSR5_22 FM(MSIOF0_RXD)
191#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
192#define GPSR5_20 FM(MSIOF0_TXD)
193#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
194#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
195#define GPSR5_17 FM(MSIOF0_SCK)
196#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
197#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
198#define GPSR5_14 F_(HTX0, IP13_19_16)
199#define GPSR5_13 F_(HRX0, IP13_15_12)
200#define GPSR5_12 F_(HSCK0, IP13_11_8)
201#define GPSR5_11 F_(RX2_A, IP13_7_4)
202#define GPSR5_10 F_(TX2_A, IP13_3_0)
203#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]204#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]205#define GPSR5_7 F_(CTS1_N, IP12_23_20)
206#define GPSR5_6 F_(TX1_A, IP12_19_16)
207#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]208#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]209#define GPSR5_3 F_(CTS0_N, IP12_7_4)
210#define GPSR5_2 F_(TX0, IP12_3_0)
211#define GPSR5_1 F_(RX0, IP11_31_28)
212#define GPSR5_0 F_(SCK0, IP11_27_24)
213
214/* GPSR6 */
215#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
216#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
217#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
218#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
219#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
220#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
221#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
222#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
223#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
224#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
225#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
226#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
227#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
228#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
229#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
230#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
231#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
232#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
233#define GPSR6_13 FM(SSI_SDATA5)
234#define GPSR6_12 FM(SSI_WS5)
235#define GPSR6_11 FM(SSI_SCK5)
236#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
237#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
238#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
239#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
240#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
241#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
242#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
243#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
244#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
245#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]246#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]247
248/* GPSR7 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]249#define GPSR7_3 FM(GP7_03)
250#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]251#define GPSR7_1 FM(AVS2)
252#define GPSR7_0 FM(AVS1)
253
254
255/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
256#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]261#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]262#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]265#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]271#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]283#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]284#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]299#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]300#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]312#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]313#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
319/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350
351/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
352#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]359#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]360#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]363#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]364#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
373#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380
381/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
382#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]399#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]400#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
402#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
403#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
404#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
405#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
406#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
408#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
409
410#define PINMUX_GPSR \
411\
412 GPSR6_31 \
413 GPSR6_30 \
414 GPSR6_29 \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]415 GPSR1_28 GPSR6_28 \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]416 GPSR1_27 GPSR6_27 \
417 GPSR1_26 GPSR6_26 \
418 GPSR1_25 GPSR5_25 GPSR6_25 \
419 GPSR1_24 GPSR5_24 GPSR6_24 \
420 GPSR1_23 GPSR5_23 GPSR6_23 \
421 GPSR1_22 GPSR5_22 GPSR6_22 \
422 GPSR1_21 GPSR5_21 GPSR6_21 \
423 GPSR1_20 GPSR5_20 GPSR6_20 \
424 GPSR1_19 GPSR5_19 GPSR6_19 \
425 GPSR1_18 GPSR5_18 GPSR6_18 \
426 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
427 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
428GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
429GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
430GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
431GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
432GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
433GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
434GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
435GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
436GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
437GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
438GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
439GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
440GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
441GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
442GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
443GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
444
445#define PINMUX_IPSR \
446\
447FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
448FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
449FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
450FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
451FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
452FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
453FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
454FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
455\
456FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
457FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
458FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
459FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
460FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
461FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
462FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
463FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
464\
465FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
466FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
467FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
468FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
469FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
470FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
471FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
472FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
473\
474FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
475FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
476FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
477FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
478FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
479FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
480FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
481FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
482\
483FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
484FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
485FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
486FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
487FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
488FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
489FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
490FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
491
492/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
493#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
494#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
495#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
496#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
497#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
498#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
499#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
500#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
501#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
502#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
503#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
504#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
505#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
506#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
507#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
508#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
509#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]510#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]511
512/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
513#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
514#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
515#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
516#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
517#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]518#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]519#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
520#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
521#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
522#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
523#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
524#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
525#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
526#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
527#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
528#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
529#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
530#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
531#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
532#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
533#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
534#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
535
536/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
537#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
538#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
539#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
540#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
541#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
542#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
543#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
544#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
545#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]546#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
547#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]548#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
549
550#define PINMUX_MOD_SELS \
551\
552MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
553 MOD_SEL2_30 \
554 MOD_SEL1_29_28_27 MOD_SEL2_29 \
555MOD_SEL0_28_27 MOD_SEL2_28_27 \
556MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
557 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
558MOD_SEL0_23 MOD_SEL1_23_22_21 \
559MOD_SEL0_22 \
560MOD_SEL0_21 MOD_SEL2_21 \
561MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
562MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
563MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
564 MOD_SEL2_17 \
565MOD_SEL0_16 MOD_SEL1_16 \
566 MOD_SEL1_15_14 \
567MOD_SEL0_14_13 \
568 MOD_SEL1_13 \
569MOD_SEL0_12 MOD_SEL1_12 \
570MOD_SEL0_11 MOD_SEL1_11 \
571MOD_SEL0_10 MOD_SEL1_10 \
572MOD_SEL0_9_8 MOD_SEL1_9 \
573MOD_SEL0_7_6 \
574 MOD_SEL1_6 \
575MOD_SEL0_5 MOD_SEL1_5 \
576MOD_SEL0_4_3 MOD_SEL1_4 \
577 MOD_SEL1_3 \
578 MOD_SEL1_2 \
579 MOD_SEL1_1 \
580 MOD_SEL1_0 MOD_SEL2_0
581
582/*
583 * These pins are not able to be muxed but have other properties
584 * that can be set, such as drive-strength or pull-up/pull-down enable.
585 */
586#define PINMUX_STATIC \
587 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
588 FM(QSPI0_IO2) FM(QSPI0_IO3) \
589 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
590 FM(QSPI1_IO2) FM(QSPI1_IO3) \
591 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
592 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
593 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
594 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]595 FM(PRESETOUT) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]596 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
597 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
598
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]599#define PINMUX_PHYS \
600 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
601
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]602enum {
603 PINMUX_RESERVED = 0,
604
605 PINMUX_DATA_BEGIN,
606 GP_ALL(DATA),
607 PINMUX_DATA_END,
608
609#define F_(x, y)
610#define FM(x) FN_##x,
611 PINMUX_FUNCTION_BEGIN,
612 GP_ALL(FN),
613 PINMUX_GPSR
614 PINMUX_IPSR
615 PINMUX_MOD_SELS
616 PINMUX_FUNCTION_END,
617#undef F_
618#undef FM
619
620#define F_(x, y)
621#define FM(x) x##_MARK,
622 PINMUX_MARK_BEGIN,
623 PINMUX_GPSR
624 PINMUX_IPSR
625 PINMUX_MOD_SELS
626 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]627 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]628 PINMUX_MARK_END,
629#undef F_
630#undef FM
631};
632
633static const u16 pinmux_data[] = {
634 PINMUX_DATA_GP_ALL(),
635
636 PINMUX_SINGLE(AVS1),
637 PINMUX_SINGLE(AVS2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]638 PINMUX_SINGLE(CLKOUT),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]639 PINMUX_SINGLE(GP7_02),
640 PINMUX_SINGLE(GP7_03),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]641 PINMUX_SINGLE(MSIOF0_RXD),
642 PINMUX_SINGLE(MSIOF0_SCK),
643 PINMUX_SINGLE(MSIOF0_TXD),
644 PINMUX_SINGLE(SSI_SCK5),
645 PINMUX_SINGLE(SSI_SDATA5),
646 PINMUX_SINGLE(SSI_WS5),
647
648 /* IPSR0 */
649 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
650 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
651
652 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
653 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
654 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
655
656 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
657 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
658 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
659
660 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
661 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
662 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
663
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]664 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
665 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
666 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
667 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
668 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]669
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]670 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
671 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
672 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]673 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]674
675 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
676 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
677 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
678 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
680 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
681 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
682
683 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
684 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
685 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
686 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
687 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
688 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
689 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
690
691 /* IPSR1 */
692 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
693 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
694 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
695 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
696 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
697 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
698
699 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
700 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]701 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
702 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
703 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
704 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
705
706 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
707 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]708 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
709 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
710 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
711 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
712
713 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
714 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]715 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
716 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
717 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
718 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
719 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
720
721 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
722 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]723 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
724 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
725
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]730 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]731
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]732 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
733 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
734 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
735 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]736
737 PINMUX_IPSR_GPSR(IP1_31_28, A0),
738 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
739 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
740 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
741 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
742 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
743
744 /* IPSR2 */
745 PINMUX_IPSR_GPSR(IP2_3_0, A1),
746 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
747 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
748 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
749 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
750 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
751
752 PINMUX_IPSR_GPSR(IP2_7_4, A2),
753 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
754 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
755 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
756 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
757 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
758
759 PINMUX_IPSR_GPSR(IP2_11_8, A3),
760 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
761 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
762 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
763 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
764 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
765
766 PINMUX_IPSR_GPSR(IP2_15_12, A4),
767 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
768 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
769 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
770 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
771 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
772
773 PINMUX_IPSR_GPSR(IP2_19_16, A5),
774 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
775 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
776 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
777 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
778 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
779 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
780
781 PINMUX_IPSR_GPSR(IP2_23_20, A6),
782 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
783 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
784 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
785 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
786 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
787 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
788
789 PINMUX_IPSR_GPSR(IP2_27_24, A7),
790 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
791 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
792 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
793 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
794 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
795 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
796
797 PINMUX_IPSR_GPSR(IP2_31_28, A8),
798 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
799 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
800 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
801 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
802 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
803 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
804
805 /* IPSR3 */
806 PINMUX_IPSR_GPSR(IP3_3_0, A9),
807 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
808 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
809 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
810
811 PINMUX_IPSR_GPSR(IP3_7_4, A10),
812 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]813 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]814 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
815
816 PINMUX_IPSR_GPSR(IP3_11_8, A11),
817 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
818 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
819 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
820 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
821 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
822 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
823 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
824 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
825
826 PINMUX_IPSR_GPSR(IP3_15_12, A12),
827 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
828 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
829 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
830 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
831 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
832
833 PINMUX_IPSR_GPSR(IP3_19_16, A13),
834 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
835 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
836 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
837 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
838 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
839
840 PINMUX_IPSR_GPSR(IP3_23_20, A14),
841 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
842 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
843 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
844 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
845 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
846
847 PINMUX_IPSR_GPSR(IP3_27_24, A15),
848 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
849 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
850 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
851 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
852 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
853
854 PINMUX_IPSR_GPSR(IP3_31_28, A16),
855 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
856 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
857 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
858
859 /* IPSR4 */
860 PINMUX_IPSR_GPSR(IP4_3_0, A17),
861 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
862 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
863 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
864
865 PINMUX_IPSR_GPSR(IP4_7_4, A18),
866 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
867 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
868 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
869
870 PINMUX_IPSR_GPSR(IP4_11_8, A19),
871 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
872 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
873 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
874
875 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
876 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
877
878 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
879 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
880 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
881
882 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
883 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
884 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
885 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
886 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
887 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
888 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
889 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
890
891 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
892 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
893 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
894 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
895 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
896 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
897
898 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
899 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
900 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
901 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
902 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
903 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
904
905 /* IPSR5 */
906 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
907 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
908 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
909 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
910 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
911 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
912 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
913
914 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
915 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]916 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]917 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
918 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
919 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
920 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
921 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
922
923 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
924 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
925 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
926 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
927
928 PINMUX_IPSR_GPSR(IP5_15_12, D0),
929 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
930 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
931 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
932 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
933
934 PINMUX_IPSR_GPSR(IP5_19_16, D1),
935 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
936 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
937 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
938 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
939
940 PINMUX_IPSR_GPSR(IP5_23_20, D2),
941 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
942 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
943 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
944
945 PINMUX_IPSR_GPSR(IP5_27_24, D3),
946 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
947 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
948 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
949
950 PINMUX_IPSR_GPSR(IP5_31_28, D4),
951 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
952 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
953 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
954
955 /* IPSR6 */
956 PINMUX_IPSR_GPSR(IP6_3_0, D5),
957 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
958 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
959 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
960
961 PINMUX_IPSR_GPSR(IP6_7_4, D6),
962 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
963 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
964 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
965
966 PINMUX_IPSR_GPSR(IP6_11_8, D7),
967 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
968 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
969 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
970
971 PINMUX_IPSR_GPSR(IP6_15_12, D8),
972 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
973 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
974 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
975 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
977
978 PINMUX_IPSR_GPSR(IP6_19_16, D9),
979 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
980 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
981 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
982 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
983
984 PINMUX_IPSR_GPSR(IP6_23_20, D10),
985 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
986 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
987 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
988 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
989 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
990 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
991
992 PINMUX_IPSR_GPSR(IP6_27_24, D11),
993 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
994 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
995 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
996 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]997 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]998 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
999
1000 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1001 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1002 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1003 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1004 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1005 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1006
1007 /* IPSR7 */
1008 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1009 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1010 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1011 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1012 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1013 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1014
1015 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1016 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1017 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1018 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1019 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1020 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1021 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1022
1023 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1024 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1025 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1026 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1027 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1028 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1029 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1030
1031 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1032 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1033 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1034
1035 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1036 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1037 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1038
1039 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1040 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1041 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1042 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1043
1044 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1045 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1046 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1047 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1048
1049 /* IPSR8 */
1050 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1051 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1052 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1053 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1054
1055 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1056 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1057 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1058 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1059
1060 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1061 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1062 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1063
1064 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1065 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1066 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1067 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1068 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1069
1070 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1071 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1072 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1073 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1074 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1075 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1076
1077 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1078 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1079 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1080 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1081 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1082 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1083
1084 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1085 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1086 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1087 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1088 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1089 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1090
1091 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1092 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1093 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1094 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1095 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1096 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1097
1098 /* IPSR9 */
1099 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1100 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1101
1102 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1103 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1104
1105 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1106 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1107
1108 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1109 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1110
1111 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1112 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1113
1114 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1115 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1116
1117 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1118 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1119 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1120
1121 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1122 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1123
1124 /* IPSR10 */
1125 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1126 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1127
1128 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1129 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1130
1131 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1132 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1133
1134 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1135 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1136
1137 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1138 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1139
1140 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1141 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1142 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1143
1144 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1145 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1146 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1147
1148 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1149 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1150 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1151
1152 /* IPSR11 */
1153 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1154 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1155 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1156
1157 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1158 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1159
1160 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1161 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1162 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1163
1164 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1165 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1166
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1167 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1168 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1169 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1170
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1171 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1172 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1173 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1174
1175 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1176 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1177 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1178 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1179 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1180 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1181 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1182 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1183 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1184 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1185
1186 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1187 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1188 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1189 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1190 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1191
1192 /* IPSR12 */
1193 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1194 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1195 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1196 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1197 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1198
1199 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1200 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1201 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1206 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1207
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1208 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1209 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1210 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1211 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1212 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1213 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1214 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1215 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1216
1217 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1218 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1219 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1220 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1221 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1222
1223 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1224 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1225 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1226 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1227 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1228
1229 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1230 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1231 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1232 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1233 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1234 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1235 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1236
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1237 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1238 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1239 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1240 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1241 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1242 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1243 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1244
1245 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1246 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1247 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1248 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1249 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1250 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1251 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1252
1253 /* IPSR13 */
1254 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1255 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1256 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1257 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1258 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1259 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1260
1261 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1262 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1263 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1264 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1265 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1266 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1267
1268 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1269 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1270 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1271 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1272 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1273 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1274 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1275 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1276
1277 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1278 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1279 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1280 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1281 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1282 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1283
1284 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1285 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1286 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1287 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1288 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1289 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1290
1291 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1292 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1293 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1294 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1295 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1296 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1297 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1298 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1299
1300 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1301 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1302 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1303 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1304 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1305 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1306 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1307
1308 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1309 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1310 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1311 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1312
1313 /* IPSR14 */
1314 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1315 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1316 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1317 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1318 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1319 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1320 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1321 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1322
1323 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1324 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1325 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1326 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1327 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1328 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1329 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1330 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1331
1332 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1333 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1334 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1335
1336 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1337 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1338 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1339 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1340
1341 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1342 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1343 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1344
1345 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1346 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1347
1348 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1349 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1350
1351 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1352 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1353
1354 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1355 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1356
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1357 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1358 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1359
1360 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1361 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1362 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1363
1364 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1365 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1366 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1367 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1368
1369 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1370 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1371 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1372 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1373 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1374 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1375 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1376
1377 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1378 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1379 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1380 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1381 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1382 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1383 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1384
1385 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1386 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1387 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1388 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1389 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1390 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1391 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1392
1393 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1394 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1395 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1396 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1397 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1398 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1399 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1400
1401 /* IPSR16 */
1402 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1403 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1404 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1405
1406 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1407 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1408 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1409
1410 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1411 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1412 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1413
1414 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1415 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1416 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1417 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1418 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1419 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1420 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1421
1422 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1423 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1424 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1425 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1426 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1427 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1428 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1429
1430 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1431 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1432 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1433 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1434 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1435 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1436 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1437 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1438
1439 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1440 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1441 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1442 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1443 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1444 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1445 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1446
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1447 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1448 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1449 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1450 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1451 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1452 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1453 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1454 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1455
1456 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1457 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1458
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1459 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1460 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1461 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1462 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1463 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1464
1465 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1466 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1467 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1468 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1469 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1470 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1471 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1472
1473 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1474 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1475 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1476 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1477 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1479
1480 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1481 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1482 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1483 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1484 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1485 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1486 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1487 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1488 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1489
1490 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1491 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1492 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1493 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1494 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1495 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1496 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1497 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1498 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1499
1500 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1501 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1502 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1503 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1504 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1505 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1506 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1507 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1508 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1509 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1510 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1511
1512 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1513 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1514 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1515 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1516 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1517 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1518 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1519 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1520 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1521
1522 /* IPSR18 */
1523 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1524 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1525 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1526 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1527 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1528 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1529 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1530 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1531 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1532
1533 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1534 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1535 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1536 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1537 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1538 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1539 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1540 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1541 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1542
1543/*
1544 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1545 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1546 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1547 * core will do the right thing and skip trying to mux the pin
1548 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1549 */
1550#define FM(x) PINMUX_DATA(x##_MARK, 0),
1551 PINMUX_STATIC
1552#undef FM
1553};
1554
1555/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1556 * Pins not associated with a GPIO port.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1557 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1558enum {
1559 GP_ASSIGN_LAST(),
1560 NOGP_ALL(),
1561};
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1562
1563static const struct sh_pfc_pin pinmux_pins[] = {
1564 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1565 PINMUX_NOGP_ALL(),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1566};
1567
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1568/* - AUDIO CLOCK ------------------------------------------------------------ */
1569static const unsigned int audio_clk_a_a_pins[] = {
1570 /* CLK A */
1571 RCAR_GP_PIN(6, 22),
1572};
1573static const unsigned int audio_clk_a_a_mux[] = {
1574 AUDIO_CLKA_A_MARK,
1575};
1576static const unsigned int audio_clk_a_b_pins[] = {
1577 /* CLK A */
1578 RCAR_GP_PIN(5, 4),
1579};
1580static const unsigned int audio_clk_a_b_mux[] = {
1581 AUDIO_CLKA_B_MARK,
1582};
1583static const unsigned int audio_clk_a_c_pins[] = {
1584 /* CLK A */
1585 RCAR_GP_PIN(5, 19),
1586};
1587static const unsigned int audio_clk_a_c_mux[] = {
1588 AUDIO_CLKA_C_MARK,
1589};
1590static const unsigned int audio_clk_b_a_pins[] = {
1591 /* CLK B */
1592 RCAR_GP_PIN(5, 12),
1593};
1594static const unsigned int audio_clk_b_a_mux[] = {
1595 AUDIO_CLKB_A_MARK,
1596};
1597static const unsigned int audio_clk_b_b_pins[] = {
1598 /* CLK B */
1599 RCAR_GP_PIN(6, 23),
1600};
1601static const unsigned int audio_clk_b_b_mux[] = {
1602 AUDIO_CLKB_B_MARK,
1603};
1604static const unsigned int audio_clk_c_a_pins[] = {
1605 /* CLK C */
1606 RCAR_GP_PIN(5, 21),
1607};
1608static const unsigned int audio_clk_c_a_mux[] = {
1609 AUDIO_CLKC_A_MARK,
1610};
1611static const unsigned int audio_clk_c_b_pins[] = {
1612 /* CLK C */
1613 RCAR_GP_PIN(5, 0),
1614};
1615static const unsigned int audio_clk_c_b_mux[] = {
1616 AUDIO_CLKC_B_MARK,
1617};
1618static const unsigned int audio_clkout_a_pins[] = {
1619 /* CLKOUT */
1620 RCAR_GP_PIN(5, 18),
1621};
1622static const unsigned int audio_clkout_a_mux[] = {
1623 AUDIO_CLKOUT_A_MARK,
1624};
1625static const unsigned int audio_clkout_b_pins[] = {
1626 /* CLKOUT */
1627 RCAR_GP_PIN(6, 28),
1628};
1629static const unsigned int audio_clkout_b_mux[] = {
1630 AUDIO_CLKOUT_B_MARK,
1631};
1632static const unsigned int audio_clkout_c_pins[] = {
1633 /* CLKOUT */
1634 RCAR_GP_PIN(5, 3),
1635};
1636static const unsigned int audio_clkout_c_mux[] = {
1637 AUDIO_CLKOUT_C_MARK,
1638};
1639static const unsigned int audio_clkout_d_pins[] = {
1640 /* CLKOUT */
1641 RCAR_GP_PIN(5, 21),
1642};
1643static const unsigned int audio_clkout_d_mux[] = {
1644 AUDIO_CLKOUT_D_MARK,
1645};
1646static const unsigned int audio_clkout1_a_pins[] = {
1647 /* CLKOUT1 */
1648 RCAR_GP_PIN(5, 15),
1649};
1650static const unsigned int audio_clkout1_a_mux[] = {
1651 AUDIO_CLKOUT1_A_MARK,
1652};
1653static const unsigned int audio_clkout1_b_pins[] = {
1654 /* CLKOUT1 */
1655 RCAR_GP_PIN(6, 29),
1656};
1657static const unsigned int audio_clkout1_b_mux[] = {
1658 AUDIO_CLKOUT1_B_MARK,
1659};
1660static const unsigned int audio_clkout2_a_pins[] = {
1661 /* CLKOUT2 */
1662 RCAR_GP_PIN(5, 16),
1663};
1664static const unsigned int audio_clkout2_a_mux[] = {
1665 AUDIO_CLKOUT2_A_MARK,
1666};
1667static const unsigned int audio_clkout2_b_pins[] = {
1668 /* CLKOUT2 */
1669 RCAR_GP_PIN(6, 30),
1670};
1671static const unsigned int audio_clkout2_b_mux[] = {
1672 AUDIO_CLKOUT2_B_MARK,
1673};
1674static const unsigned int audio_clkout3_a_pins[] = {
1675 /* CLKOUT3 */
1676 RCAR_GP_PIN(5, 19),
1677};
1678static const unsigned int audio_clkout3_a_mux[] = {
1679 AUDIO_CLKOUT3_A_MARK,
1680};
1681static const unsigned int audio_clkout3_b_pins[] = {
1682 /* CLKOUT3 */
1683 RCAR_GP_PIN(6, 31),
1684};
1685static const unsigned int audio_clkout3_b_mux[] = {
1686 AUDIO_CLKOUT3_B_MARK,
1687};
1688
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1689/* - EtherAVB --------------------------------------------------------------- */
1690static const unsigned int avb_link_pins[] = {
1691 /* AVB_LINK */
1692 RCAR_GP_PIN(2, 12),
1693};
1694static const unsigned int avb_link_mux[] = {
1695 AVB_LINK_MARK,
1696};
1697static const unsigned int avb_magic_pins[] = {
1698 /* AVB_MAGIC_ */
1699 RCAR_GP_PIN(2, 10),
1700};
1701static const unsigned int avb_magic_mux[] = {
1702 AVB_MAGIC_MARK,
1703};
1704static const unsigned int avb_phy_int_pins[] = {
1705 /* AVB_PHY_INT */
1706 RCAR_GP_PIN(2, 11),
1707};
1708static const unsigned int avb_phy_int_mux[] = {
1709 AVB_PHY_INT_MARK,
1710};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1711static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1712 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1713 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1714};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1715static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1716 AVB_MDC_MARK, AVB_MDIO_MARK,
1717};
1718static const unsigned int avb_mii_pins[] = {
1719 /*
1720 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1721 * AVB_TD1, AVB_TD2, AVB_TD3,
1722 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1723 * AVB_RD1, AVB_RD2, AVB_RD3,
1724 * AVB_TXCREFCLK
1725 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1726 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1727 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1728 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1729 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1730 PIN_AVB_TXCREFCLK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1731};
1732static const unsigned int avb_mii_mux[] = {
1733 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1734 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1735 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1736 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1737 AVB_TXCREFCLK_MARK,
1738};
1739static const unsigned int avb_avtp_pps_pins[] = {
1740 /* AVB_AVTP_PPS */
1741 RCAR_GP_PIN(2, 6),
1742};
1743static const unsigned int avb_avtp_pps_mux[] = {
1744 AVB_AVTP_PPS_MARK,
1745};
1746static const unsigned int avb_avtp_match_a_pins[] = {
1747 /* AVB_AVTP_MATCH_A */
1748 RCAR_GP_PIN(2, 13),
1749};
1750static const unsigned int avb_avtp_match_a_mux[] = {
1751 AVB_AVTP_MATCH_A_MARK,
1752};
1753static const unsigned int avb_avtp_capture_a_pins[] = {
1754 /* AVB_AVTP_CAPTURE_A */
1755 RCAR_GP_PIN(2, 14),
1756};
1757static const unsigned int avb_avtp_capture_a_mux[] = {
1758 AVB_AVTP_CAPTURE_A_MARK,
1759};
1760static const unsigned int avb_avtp_match_b_pins[] = {
1761 /* AVB_AVTP_MATCH_B */
1762 RCAR_GP_PIN(1, 8),
1763};
1764static const unsigned int avb_avtp_match_b_mux[] = {
1765 AVB_AVTP_MATCH_B_MARK,
1766};
1767static const unsigned int avb_avtp_capture_b_pins[] = {
1768 /* AVB_AVTP_CAPTURE_B */
1769 RCAR_GP_PIN(1, 11),
1770};
1771static const unsigned int avb_avtp_capture_b_mux[] = {
1772 AVB_AVTP_CAPTURE_B_MARK,
1773};
1774
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1775/* - CAN ------------------------------------------------------------------ */
1776static const unsigned int can0_data_a_pins[] = {
1777 /* TX, RX */
1778 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1779};
1780static const unsigned int can0_data_a_mux[] = {
1781 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1782};
1783static const unsigned int can0_data_b_pins[] = {
1784 /* TX, RX */
1785 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1786};
1787static const unsigned int can0_data_b_mux[] = {
1788 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1789};
1790static const unsigned int can1_data_pins[] = {
1791 /* TX, RX */
1792 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1793};
1794static const unsigned int can1_data_mux[] = {
1795 CAN1_TX_MARK, CAN1_RX_MARK,
1796};
1797
1798/* - CAN Clock -------------------------------------------------------------- */
1799static const unsigned int can_clk_pins[] = {
1800 /* CLK */
1801 RCAR_GP_PIN(1, 25),
1802};
1803static const unsigned int can_clk_mux[] = {
1804 CAN_CLK_MARK,
1805};
1806
1807/* - CAN FD --------------------------------------------------------------- */
1808static const unsigned int canfd0_data_a_pins[] = {
1809 /* TX, RX */
1810 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1811};
1812static const unsigned int canfd0_data_a_mux[] = {
1813 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1814};
1815static const unsigned int canfd0_data_b_pins[] = {
1816 /* TX, RX */
1817 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1818};
1819static const unsigned int canfd0_data_b_mux[] = {
1820 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1821};
1822static const unsigned int canfd1_data_pins[] = {
1823 /* TX, RX */
1824 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1825};
1826static const unsigned int canfd1_data_mux[] = {
1827 CANFD1_TX_MARK, CANFD1_RX_MARK,
1828};
1829
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]1830#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1831/* - DRIF0 --------------------------------------------------------------- */
1832static const unsigned int drif0_ctrl_a_pins[] = {
1833 /* CLK, SYNC */
1834 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1835};
1836static const unsigned int drif0_ctrl_a_mux[] = {
1837 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1838};
1839static const unsigned int drif0_data0_a_pins[] = {
1840 /* D0 */
1841 RCAR_GP_PIN(6, 10),
1842};
1843static const unsigned int drif0_data0_a_mux[] = {
1844 RIF0_D0_A_MARK,
1845};
1846static const unsigned int drif0_data1_a_pins[] = {
1847 /* D1 */
1848 RCAR_GP_PIN(6, 7),
1849};
1850static const unsigned int drif0_data1_a_mux[] = {
1851 RIF0_D1_A_MARK,
1852};
1853static const unsigned int drif0_ctrl_b_pins[] = {
1854 /* CLK, SYNC */
1855 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1856};
1857static const unsigned int drif0_ctrl_b_mux[] = {
1858 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1859};
1860static const unsigned int drif0_data0_b_pins[] = {
1861 /* D0 */
1862 RCAR_GP_PIN(5, 1),
1863};
1864static const unsigned int drif0_data0_b_mux[] = {
1865 RIF0_D0_B_MARK,
1866};
1867static const unsigned int drif0_data1_b_pins[] = {
1868 /* D1 */
1869 RCAR_GP_PIN(5, 2),
1870};
1871static const unsigned int drif0_data1_b_mux[] = {
1872 RIF0_D1_B_MARK,
1873};
1874static const unsigned int drif0_ctrl_c_pins[] = {
1875 /* CLK, SYNC */
1876 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1877};
1878static const unsigned int drif0_ctrl_c_mux[] = {
1879 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1880};
1881static const unsigned int drif0_data0_c_pins[] = {
1882 /* D0 */
1883 RCAR_GP_PIN(5, 13),
1884};
1885static const unsigned int drif0_data0_c_mux[] = {
1886 RIF0_D0_C_MARK,
1887};
1888static const unsigned int drif0_data1_c_pins[] = {
1889 /* D1 */
1890 RCAR_GP_PIN(5, 14),
1891};
1892static const unsigned int drif0_data1_c_mux[] = {
1893 RIF0_D1_C_MARK,
1894};
1895/* - DRIF1 --------------------------------------------------------------- */
1896static const unsigned int drif1_ctrl_a_pins[] = {
1897 /* CLK, SYNC */
1898 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1899};
1900static const unsigned int drif1_ctrl_a_mux[] = {
1901 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1902};
1903static const unsigned int drif1_data0_a_pins[] = {
1904 /* D0 */
1905 RCAR_GP_PIN(6, 19),
1906};
1907static const unsigned int drif1_data0_a_mux[] = {
1908 RIF1_D0_A_MARK,
1909};
1910static const unsigned int drif1_data1_a_pins[] = {
1911 /* D1 */
1912 RCAR_GP_PIN(6, 20),
1913};
1914static const unsigned int drif1_data1_a_mux[] = {
1915 RIF1_D1_A_MARK,
1916};
1917static const unsigned int drif1_ctrl_b_pins[] = {
1918 /* CLK, SYNC */
1919 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1920};
1921static const unsigned int drif1_ctrl_b_mux[] = {
1922 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1923};
1924static const unsigned int drif1_data0_b_pins[] = {
1925 /* D0 */
1926 RCAR_GP_PIN(5, 7),
1927};
1928static const unsigned int drif1_data0_b_mux[] = {
1929 RIF1_D0_B_MARK,
1930};
1931static const unsigned int drif1_data1_b_pins[] = {
1932 /* D1 */
1933 RCAR_GP_PIN(5, 8),
1934};
1935static const unsigned int drif1_data1_b_mux[] = {
1936 RIF1_D1_B_MARK,
1937};
1938static const unsigned int drif1_ctrl_c_pins[] = {
1939 /* CLK, SYNC */
1940 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1941};
1942static const unsigned int drif1_ctrl_c_mux[] = {
1943 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1944};
1945static const unsigned int drif1_data0_c_pins[] = {
1946 /* D0 */
1947 RCAR_GP_PIN(5, 6),
1948};
1949static const unsigned int drif1_data0_c_mux[] = {
1950 RIF1_D0_C_MARK,
1951};
1952static const unsigned int drif1_data1_c_pins[] = {
1953 /* D1 */
1954 RCAR_GP_PIN(5, 10),
1955};
1956static const unsigned int drif1_data1_c_mux[] = {
1957 RIF1_D1_C_MARK,
1958};
1959/* - DRIF2 --------------------------------------------------------------- */
1960static const unsigned int drif2_ctrl_a_pins[] = {
1961 /* CLK, SYNC */
1962 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1963};
1964static const unsigned int drif2_ctrl_a_mux[] = {
1965 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1966};
1967static const unsigned int drif2_data0_a_pins[] = {
1968 /* D0 */
1969 RCAR_GP_PIN(6, 7),
1970};
1971static const unsigned int drif2_data0_a_mux[] = {
1972 RIF2_D0_A_MARK,
1973};
1974static const unsigned int drif2_data1_a_pins[] = {
1975 /* D1 */
1976 RCAR_GP_PIN(6, 10),
1977};
1978static const unsigned int drif2_data1_a_mux[] = {
1979 RIF2_D1_A_MARK,
1980};
1981static const unsigned int drif2_ctrl_b_pins[] = {
1982 /* CLK, SYNC */
1983 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1984};
1985static const unsigned int drif2_ctrl_b_mux[] = {
1986 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1987};
1988static const unsigned int drif2_data0_b_pins[] = {
1989 /* D0 */
1990 RCAR_GP_PIN(6, 30),
1991};
1992static const unsigned int drif2_data0_b_mux[] = {
1993 RIF2_D0_B_MARK,
1994};
1995static const unsigned int drif2_data1_b_pins[] = {
1996 /* D1 */
1997 RCAR_GP_PIN(6, 31),
1998};
1999static const unsigned int drif2_data1_b_mux[] = {
2000 RIF2_D1_B_MARK,
2001};
2002/* - DRIF3 --------------------------------------------------------------- */
2003static const unsigned int drif3_ctrl_a_pins[] = {
2004 /* CLK, SYNC */
2005 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2006};
2007static const unsigned int drif3_ctrl_a_mux[] = {
2008 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2009};
2010static const unsigned int drif3_data0_a_pins[] = {
2011 /* D0 */
2012 RCAR_GP_PIN(6, 19),
2013};
2014static const unsigned int drif3_data0_a_mux[] = {
2015 RIF3_D0_A_MARK,
2016};
2017static const unsigned int drif3_data1_a_pins[] = {
2018 /* D1 */
2019 RCAR_GP_PIN(6, 20),
2020};
2021static const unsigned int drif3_data1_a_mux[] = {
2022 RIF3_D1_A_MARK,
2023};
2024static const unsigned int drif3_ctrl_b_pins[] = {
2025 /* CLK, SYNC */
2026 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2027};
2028static const unsigned int drif3_ctrl_b_mux[] = {
2029 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2030};
2031static const unsigned int drif3_data0_b_pins[] = {
2032 /* D0 */
2033 RCAR_GP_PIN(6, 28),
2034};
2035static const unsigned int drif3_data0_b_mux[] = {
2036 RIF3_D0_B_MARK,
2037};
2038static const unsigned int drif3_data1_b_pins[] = {
2039 /* D1 */
2040 RCAR_GP_PIN(6, 29),
2041};
2042static const unsigned int drif3_data1_b_mux[] = {
2043 RIF3_D1_B_MARK,
2044};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]2045#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2046
2047/* - DU --------------------------------------------------------------------- */
2048static const unsigned int du_rgb666_pins[] = {
2049 /* R[7:2], G[7:2], B[7:2] */
2050 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2051 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2052 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2053 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2054 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2055 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2056};
2057static const unsigned int du_rgb666_mux[] = {
2058 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2059 DU_DR3_MARK, DU_DR2_MARK,
2060 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2061 DU_DG3_MARK, DU_DG2_MARK,
2062 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2063 DU_DB3_MARK, DU_DB2_MARK,
2064};
2065static const unsigned int du_rgb888_pins[] = {
2066 /* R[7:0], G[7:0], B[7:0] */
2067 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2068 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2069 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2070 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2071 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2072 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2073 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2074 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2075 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2076};
2077static const unsigned int du_rgb888_mux[] = {
2078 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2079 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2080 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2081 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2082 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2083 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2084};
2085static const unsigned int du_clk_out_0_pins[] = {
2086 /* CLKOUT */
2087 RCAR_GP_PIN(1, 27),
2088};
2089static const unsigned int du_clk_out_0_mux[] = {
2090 DU_DOTCLKOUT0_MARK
2091};
2092static const unsigned int du_clk_out_1_pins[] = {
2093 /* CLKOUT */
2094 RCAR_GP_PIN(2, 3),
2095};
2096static const unsigned int du_clk_out_1_mux[] = {
2097 DU_DOTCLKOUT1_MARK
2098};
2099static const unsigned int du_sync_pins[] = {
2100 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2101 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2102};
2103static const unsigned int du_sync_mux[] = {
2104 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2105};
2106static const unsigned int du_oddf_pins[] = {
2107 /* EXDISP/EXODDF/EXCDE */
2108 RCAR_GP_PIN(2, 2),
2109};
2110static const unsigned int du_oddf_mux[] = {
2111 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2112};
2113static const unsigned int du_cde_pins[] = {
2114 /* CDE */
2115 RCAR_GP_PIN(2, 0),
2116};
2117static const unsigned int du_cde_mux[] = {
2118 DU_CDE_MARK,
2119};
2120static const unsigned int du_disp_pins[] = {
2121 /* DISP */
2122 RCAR_GP_PIN(2, 1),
2123};
2124static const unsigned int du_disp_mux[] = {
2125 DU_DISP_MARK,
2126};
2127
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2128/* - HSCIF0 ----------------------------------------------------------------- */
2129static const unsigned int hscif0_data_pins[] = {
2130 /* RX, TX */
2131 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2132};
2133static const unsigned int hscif0_data_mux[] = {
2134 HRX0_MARK, HTX0_MARK,
2135};
2136static const unsigned int hscif0_clk_pins[] = {
2137 /* SCK */
2138 RCAR_GP_PIN(5, 12),
2139};
2140static const unsigned int hscif0_clk_mux[] = {
2141 HSCK0_MARK,
2142};
2143static const unsigned int hscif0_ctrl_pins[] = {
2144 /* RTS, CTS */
2145 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2146};
2147static const unsigned int hscif0_ctrl_mux[] = {
2148 HRTS0_N_MARK, HCTS0_N_MARK,
2149};
2150/* - HSCIF1 ----------------------------------------------------------------- */
2151static const unsigned int hscif1_data_a_pins[] = {
2152 /* RX, TX */
2153 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2154};
2155static const unsigned int hscif1_data_a_mux[] = {
2156 HRX1_A_MARK, HTX1_A_MARK,
2157};
2158static const unsigned int hscif1_clk_a_pins[] = {
2159 /* SCK */
2160 RCAR_GP_PIN(6, 21),
2161};
2162static const unsigned int hscif1_clk_a_mux[] = {
2163 HSCK1_A_MARK,
2164};
2165static const unsigned int hscif1_ctrl_a_pins[] = {
2166 /* RTS, CTS */
2167 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2168};
2169static const unsigned int hscif1_ctrl_a_mux[] = {
2170 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2171};
2172
2173static const unsigned int hscif1_data_b_pins[] = {
2174 /* RX, TX */
2175 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2176};
2177static const unsigned int hscif1_data_b_mux[] = {
2178 HRX1_B_MARK, HTX1_B_MARK,
2179};
2180static const unsigned int hscif1_clk_b_pins[] = {
2181 /* SCK */
2182 RCAR_GP_PIN(5, 0),
2183};
2184static const unsigned int hscif1_clk_b_mux[] = {
2185 HSCK1_B_MARK,
2186};
2187static const unsigned int hscif1_ctrl_b_pins[] = {
2188 /* RTS, CTS */
2189 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2190};
2191static const unsigned int hscif1_ctrl_b_mux[] = {
2192 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2193};
2194/* - HSCIF2 ----------------------------------------------------------------- */
2195static const unsigned int hscif2_data_a_pins[] = {
2196 /* RX, TX */
2197 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2198};
2199static const unsigned int hscif2_data_a_mux[] = {
2200 HRX2_A_MARK, HTX2_A_MARK,
2201};
2202static const unsigned int hscif2_clk_a_pins[] = {
2203 /* SCK */
2204 RCAR_GP_PIN(6, 10),
2205};
2206static const unsigned int hscif2_clk_a_mux[] = {
2207 HSCK2_A_MARK,
2208};
2209static const unsigned int hscif2_ctrl_a_pins[] = {
2210 /* RTS, CTS */
2211 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2212};
2213static const unsigned int hscif2_ctrl_a_mux[] = {
2214 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2215};
2216
2217static const unsigned int hscif2_data_b_pins[] = {
2218 /* RX, TX */
2219 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2220};
2221static const unsigned int hscif2_data_b_mux[] = {
2222 HRX2_B_MARK, HTX2_B_MARK,
2223};
2224static const unsigned int hscif2_clk_b_pins[] = {
2225 /* SCK */
2226 RCAR_GP_PIN(6, 21),
2227};
2228static const unsigned int hscif2_clk_b_mux[] = {
2229 HSCK2_B_MARK,
2230};
2231static const unsigned int hscif2_ctrl_b_pins[] = {
2232 /* RTS, CTS */
2233 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2234};
2235static const unsigned int hscif2_ctrl_b_mux[] = {
2236 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2237};
2238
2239static const unsigned int hscif2_data_c_pins[] = {
2240 /* RX, TX */
2241 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2242};
2243static const unsigned int hscif2_data_c_mux[] = {
2244 HRX2_C_MARK, HTX2_C_MARK,
2245};
2246static const unsigned int hscif2_clk_c_pins[] = {
2247 /* SCK */
2248 RCAR_GP_PIN(6, 24),
2249};
2250static const unsigned int hscif2_clk_c_mux[] = {
2251 HSCK2_C_MARK,
2252};
2253static const unsigned int hscif2_ctrl_c_pins[] = {
2254 /* RTS, CTS */
2255 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2256};
2257static const unsigned int hscif2_ctrl_c_mux[] = {
2258 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2259};
2260/* - HSCIF3 ----------------------------------------------------------------- */
2261static const unsigned int hscif3_data_a_pins[] = {
2262 /* RX, TX */
2263 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2264};
2265static const unsigned int hscif3_data_a_mux[] = {
2266 HRX3_A_MARK, HTX3_A_MARK,
2267};
2268static const unsigned int hscif3_clk_pins[] = {
2269 /* SCK */
2270 RCAR_GP_PIN(1, 22),
2271};
2272static const unsigned int hscif3_clk_mux[] = {
2273 HSCK3_MARK,
2274};
2275static const unsigned int hscif3_ctrl_pins[] = {
2276 /* RTS, CTS */
2277 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2278};
2279static const unsigned int hscif3_ctrl_mux[] = {
2280 HRTS3_N_MARK, HCTS3_N_MARK,
2281};
2282
2283static const unsigned int hscif3_data_b_pins[] = {
2284 /* RX, TX */
2285 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2286};
2287static const unsigned int hscif3_data_b_mux[] = {
2288 HRX3_B_MARK, HTX3_B_MARK,
2289};
2290static const unsigned int hscif3_data_c_pins[] = {
2291 /* RX, TX */
2292 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2293};
2294static const unsigned int hscif3_data_c_mux[] = {
2295 HRX3_C_MARK, HTX3_C_MARK,
2296};
2297static const unsigned int hscif3_data_d_pins[] = {
2298 /* RX, TX */
2299 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2300};
2301static const unsigned int hscif3_data_d_mux[] = {
2302 HRX3_D_MARK, HTX3_D_MARK,
2303};
2304/* - HSCIF4 ----------------------------------------------------------------- */
2305static const unsigned int hscif4_data_a_pins[] = {
2306 /* RX, TX */
2307 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2308};
2309static const unsigned int hscif4_data_a_mux[] = {
2310 HRX4_A_MARK, HTX4_A_MARK,
2311};
2312static const unsigned int hscif4_clk_pins[] = {
2313 /* SCK */
2314 RCAR_GP_PIN(1, 11),
2315};
2316static const unsigned int hscif4_clk_mux[] = {
2317 HSCK4_MARK,
2318};
2319static const unsigned int hscif4_ctrl_pins[] = {
2320 /* RTS, CTS */
2321 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2322};
2323static const unsigned int hscif4_ctrl_mux[] = {
2324 HRTS4_N_MARK, HCTS4_N_MARK,
2325};
2326
2327static const unsigned int hscif4_data_b_pins[] = {
2328 /* RX, TX */
2329 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2330};
2331static const unsigned int hscif4_data_b_mux[] = {
2332 HRX4_B_MARK, HTX4_B_MARK,
2333};
2334
2335/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2336static const unsigned int i2c0_pins[] = {
2337 /* SCL, SDA */
2338 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2339};
2340
2341static const unsigned int i2c0_mux[] = {
2342 SCL0_MARK, SDA0_MARK,
2343};
2344
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2345static const unsigned int i2c1_a_pins[] = {
2346 /* SDA, SCL */
2347 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2348};
2349static const unsigned int i2c1_a_mux[] = {
2350 SDA1_A_MARK, SCL1_A_MARK,
2351};
2352static const unsigned int i2c1_b_pins[] = {
2353 /* SDA, SCL */
2354 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2355};
2356static const unsigned int i2c1_b_mux[] = {
2357 SDA1_B_MARK, SCL1_B_MARK,
2358};
2359static const unsigned int i2c2_a_pins[] = {
2360 /* SDA, SCL */
2361 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2362};
2363static const unsigned int i2c2_a_mux[] = {
2364 SDA2_A_MARK, SCL2_A_MARK,
2365};
2366static const unsigned int i2c2_b_pins[] = {
2367 /* SDA, SCL */
2368 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2369};
2370static const unsigned int i2c2_b_mux[] = {
2371 SDA2_B_MARK, SCL2_B_MARK,
2372};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2373
2374static const unsigned int i2c3_pins[] = {
2375 /* SCL, SDA */
2376 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2377};
2378
2379static const unsigned int i2c3_mux[] = {
2380 SCL3_MARK, SDA3_MARK,
2381};
2382
2383static const unsigned int i2c5_pins[] = {
2384 /* SCL, SDA */
2385 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2386};
2387
2388static const unsigned int i2c5_mux[] = {
2389 SCL5_MARK, SDA5_MARK,
2390};
2391
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2392static const unsigned int i2c6_a_pins[] = {
2393 /* SDA, SCL */
2394 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2395};
2396static const unsigned int i2c6_a_mux[] = {
2397 SDA6_A_MARK, SCL6_A_MARK,
2398};
2399static const unsigned int i2c6_b_pins[] = {
2400 /* SDA, SCL */
2401 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2402};
2403static const unsigned int i2c6_b_mux[] = {
2404 SDA6_B_MARK, SCL6_B_MARK,
2405};
2406static const unsigned int i2c6_c_pins[] = {
2407 /* SDA, SCL */
2408 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2409};
2410static const unsigned int i2c6_c_mux[] = {
2411 SDA6_C_MARK, SCL6_C_MARK,
2412};
2413
2414/* - INTC-EX ---------------------------------------------------------------- */
2415static const unsigned int intc_ex_irq0_pins[] = {
2416 /* IRQ0 */
2417 RCAR_GP_PIN(2, 0),
2418};
2419static const unsigned int intc_ex_irq0_mux[] = {
2420 IRQ0_MARK,
2421};
2422static const unsigned int intc_ex_irq1_pins[] = {
2423 /* IRQ1 */
2424 RCAR_GP_PIN(2, 1),
2425};
2426static const unsigned int intc_ex_irq1_mux[] = {
2427 IRQ1_MARK,
2428};
2429static const unsigned int intc_ex_irq2_pins[] = {
2430 /* IRQ2 */
2431 RCAR_GP_PIN(2, 2),
2432};
2433static const unsigned int intc_ex_irq2_mux[] = {
2434 IRQ2_MARK,
2435};
2436static const unsigned int intc_ex_irq3_pins[] = {
2437 /* IRQ3 */
2438 RCAR_GP_PIN(2, 3),
2439};
2440static const unsigned int intc_ex_irq3_mux[] = {
2441 IRQ3_MARK,
2442};
2443static const unsigned int intc_ex_irq4_pins[] = {
2444 /* IRQ4 */
2445 RCAR_GP_PIN(2, 4),
2446};
2447static const unsigned int intc_ex_irq4_mux[] = {
2448 IRQ4_MARK,
2449};
2450static const unsigned int intc_ex_irq5_pins[] = {
2451 /* IRQ5 */
2452 RCAR_GP_PIN(2, 5),
2453};
2454static const unsigned int intc_ex_irq5_mux[] = {
2455 IRQ5_MARK,
2456};
2457
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]2458#ifdef CONFIG_PINCTRL_PFC_R8A77951
2459/* - MLB+ ------------------------------------------------------------------- */
2460static const unsigned int mlb_3pin_pins[] = {
2461 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2462};
2463static const unsigned int mlb_3pin_mux[] = {
2464 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2465};
2466#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2467
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2468/* - MSIOF0 ----------------------------------------------------------------- */
2469static const unsigned int msiof0_clk_pins[] = {
2470 /* SCK */
2471 RCAR_GP_PIN(5, 17),
2472};
2473static const unsigned int msiof0_clk_mux[] = {
2474 MSIOF0_SCK_MARK,
2475};
2476static const unsigned int msiof0_sync_pins[] = {
2477 /* SYNC */
2478 RCAR_GP_PIN(5, 18),
2479};
2480static const unsigned int msiof0_sync_mux[] = {
2481 MSIOF0_SYNC_MARK,
2482};
2483static const unsigned int msiof0_ss1_pins[] = {
2484 /* SS1 */
2485 RCAR_GP_PIN(5, 19),
2486};
2487static const unsigned int msiof0_ss1_mux[] = {
2488 MSIOF0_SS1_MARK,
2489};
2490static const unsigned int msiof0_ss2_pins[] = {
2491 /* SS2 */
2492 RCAR_GP_PIN(5, 21),
2493};
2494static const unsigned int msiof0_ss2_mux[] = {
2495 MSIOF0_SS2_MARK,
2496};
2497static const unsigned int msiof0_txd_pins[] = {
2498 /* TXD */
2499 RCAR_GP_PIN(5, 20),
2500};
2501static const unsigned int msiof0_txd_mux[] = {
2502 MSIOF0_TXD_MARK,
2503};
2504static const unsigned int msiof0_rxd_pins[] = {
2505 /* RXD */
2506 RCAR_GP_PIN(5, 22),
2507};
2508static const unsigned int msiof0_rxd_mux[] = {
2509 MSIOF0_RXD_MARK,
2510};
2511/* - MSIOF1 ----------------------------------------------------------------- */
2512static const unsigned int msiof1_clk_a_pins[] = {
2513 /* SCK */
2514 RCAR_GP_PIN(6, 8),
2515};
2516static const unsigned int msiof1_clk_a_mux[] = {
2517 MSIOF1_SCK_A_MARK,
2518};
2519static const unsigned int msiof1_sync_a_pins[] = {
2520 /* SYNC */
2521 RCAR_GP_PIN(6, 9),
2522};
2523static const unsigned int msiof1_sync_a_mux[] = {
2524 MSIOF1_SYNC_A_MARK,
2525};
2526static const unsigned int msiof1_ss1_a_pins[] = {
2527 /* SS1 */
2528 RCAR_GP_PIN(6, 5),
2529};
2530static const unsigned int msiof1_ss1_a_mux[] = {
2531 MSIOF1_SS1_A_MARK,
2532};
2533static const unsigned int msiof1_ss2_a_pins[] = {
2534 /* SS2 */
2535 RCAR_GP_PIN(6, 6),
2536};
2537static const unsigned int msiof1_ss2_a_mux[] = {
2538 MSIOF1_SS2_A_MARK,
2539};
2540static const unsigned int msiof1_txd_a_pins[] = {
2541 /* TXD */
2542 RCAR_GP_PIN(6, 7),
2543};
2544static const unsigned int msiof1_txd_a_mux[] = {
2545 MSIOF1_TXD_A_MARK,
2546};
2547static const unsigned int msiof1_rxd_a_pins[] = {
2548 /* RXD */
2549 RCAR_GP_PIN(6, 10),
2550};
2551static const unsigned int msiof1_rxd_a_mux[] = {
2552 MSIOF1_RXD_A_MARK,
2553};
2554static const unsigned int msiof1_clk_b_pins[] = {
2555 /* SCK */
2556 RCAR_GP_PIN(5, 9),
2557};
2558static const unsigned int msiof1_clk_b_mux[] = {
2559 MSIOF1_SCK_B_MARK,
2560};
2561static const unsigned int msiof1_sync_b_pins[] = {
2562 /* SYNC */
2563 RCAR_GP_PIN(5, 3),
2564};
2565static const unsigned int msiof1_sync_b_mux[] = {
2566 MSIOF1_SYNC_B_MARK,
2567};
2568static const unsigned int msiof1_ss1_b_pins[] = {
2569 /* SS1 */
2570 RCAR_GP_PIN(5, 4),
2571};
2572static const unsigned int msiof1_ss1_b_mux[] = {
2573 MSIOF1_SS1_B_MARK,
2574};
2575static const unsigned int msiof1_ss2_b_pins[] = {
2576 /* SS2 */
2577 RCAR_GP_PIN(5, 0),
2578};
2579static const unsigned int msiof1_ss2_b_mux[] = {
2580 MSIOF1_SS2_B_MARK,
2581};
2582static const unsigned int msiof1_txd_b_pins[] = {
2583 /* TXD */
2584 RCAR_GP_PIN(5, 8),
2585};
2586static const unsigned int msiof1_txd_b_mux[] = {
2587 MSIOF1_TXD_B_MARK,
2588};
2589static const unsigned int msiof1_rxd_b_pins[] = {
2590 /* RXD */
2591 RCAR_GP_PIN(5, 7),
2592};
2593static const unsigned int msiof1_rxd_b_mux[] = {
2594 MSIOF1_RXD_B_MARK,
2595};
2596static const unsigned int msiof1_clk_c_pins[] = {
2597 /* SCK */
2598 RCAR_GP_PIN(6, 17),
2599};
2600static const unsigned int msiof1_clk_c_mux[] = {
2601 MSIOF1_SCK_C_MARK,
2602};
2603static const unsigned int msiof1_sync_c_pins[] = {
2604 /* SYNC */
2605 RCAR_GP_PIN(6, 18),
2606};
2607static const unsigned int msiof1_sync_c_mux[] = {
2608 MSIOF1_SYNC_C_MARK,
2609};
2610static const unsigned int msiof1_ss1_c_pins[] = {
2611 /* SS1 */
2612 RCAR_GP_PIN(6, 21),
2613};
2614static const unsigned int msiof1_ss1_c_mux[] = {
2615 MSIOF1_SS1_C_MARK,
2616};
2617static const unsigned int msiof1_ss2_c_pins[] = {
2618 /* SS2 */
2619 RCAR_GP_PIN(6, 27),
2620};
2621static const unsigned int msiof1_ss2_c_mux[] = {
2622 MSIOF1_SS2_C_MARK,
2623};
2624static const unsigned int msiof1_txd_c_pins[] = {
2625 /* TXD */
2626 RCAR_GP_PIN(6, 20),
2627};
2628static const unsigned int msiof1_txd_c_mux[] = {
2629 MSIOF1_TXD_C_MARK,
2630};
2631static const unsigned int msiof1_rxd_c_pins[] = {
2632 /* RXD */
2633 RCAR_GP_PIN(6, 19),
2634};
2635static const unsigned int msiof1_rxd_c_mux[] = {
2636 MSIOF1_RXD_C_MARK,
2637};
2638static const unsigned int msiof1_clk_d_pins[] = {
2639 /* SCK */
2640 RCAR_GP_PIN(5, 12),
2641};
2642static const unsigned int msiof1_clk_d_mux[] = {
2643 MSIOF1_SCK_D_MARK,
2644};
2645static const unsigned int msiof1_sync_d_pins[] = {
2646 /* SYNC */
2647 RCAR_GP_PIN(5, 15),
2648};
2649static const unsigned int msiof1_sync_d_mux[] = {
2650 MSIOF1_SYNC_D_MARK,
2651};
2652static const unsigned int msiof1_ss1_d_pins[] = {
2653 /* SS1 */
2654 RCAR_GP_PIN(5, 16),
2655};
2656static const unsigned int msiof1_ss1_d_mux[] = {
2657 MSIOF1_SS1_D_MARK,
2658};
2659static const unsigned int msiof1_ss2_d_pins[] = {
2660 /* SS2 */
2661 RCAR_GP_PIN(5, 21),
2662};
2663static const unsigned int msiof1_ss2_d_mux[] = {
2664 MSIOF1_SS2_D_MARK,
2665};
2666static const unsigned int msiof1_txd_d_pins[] = {
2667 /* TXD */
2668 RCAR_GP_PIN(5, 14),
2669};
2670static const unsigned int msiof1_txd_d_mux[] = {
2671 MSIOF1_TXD_D_MARK,
2672};
2673static const unsigned int msiof1_rxd_d_pins[] = {
2674 /* RXD */
2675 RCAR_GP_PIN(5, 13),
2676};
2677static const unsigned int msiof1_rxd_d_mux[] = {
2678 MSIOF1_RXD_D_MARK,
2679};
2680static const unsigned int msiof1_clk_e_pins[] = {
2681 /* SCK */
2682 RCAR_GP_PIN(3, 0),
2683};
2684static const unsigned int msiof1_clk_e_mux[] = {
2685 MSIOF1_SCK_E_MARK,
2686};
2687static const unsigned int msiof1_sync_e_pins[] = {
2688 /* SYNC */
2689 RCAR_GP_PIN(3, 1),
2690};
2691static const unsigned int msiof1_sync_e_mux[] = {
2692 MSIOF1_SYNC_E_MARK,
2693};
2694static const unsigned int msiof1_ss1_e_pins[] = {
2695 /* SS1 */
2696 RCAR_GP_PIN(3, 4),
2697};
2698static const unsigned int msiof1_ss1_e_mux[] = {
2699 MSIOF1_SS1_E_MARK,
2700};
2701static const unsigned int msiof1_ss2_e_pins[] = {
2702 /* SS2 */
2703 RCAR_GP_PIN(3, 5),
2704};
2705static const unsigned int msiof1_ss2_e_mux[] = {
2706 MSIOF1_SS2_E_MARK,
2707};
2708static const unsigned int msiof1_txd_e_pins[] = {
2709 /* TXD */
2710 RCAR_GP_PIN(3, 3),
2711};
2712static const unsigned int msiof1_txd_e_mux[] = {
2713 MSIOF1_TXD_E_MARK,
2714};
2715static const unsigned int msiof1_rxd_e_pins[] = {
2716 /* RXD */
2717 RCAR_GP_PIN(3, 2),
2718};
2719static const unsigned int msiof1_rxd_e_mux[] = {
2720 MSIOF1_RXD_E_MARK,
2721};
2722static const unsigned int msiof1_clk_f_pins[] = {
2723 /* SCK */
2724 RCAR_GP_PIN(5, 23),
2725};
2726static const unsigned int msiof1_clk_f_mux[] = {
2727 MSIOF1_SCK_F_MARK,
2728};
2729static const unsigned int msiof1_sync_f_pins[] = {
2730 /* SYNC */
2731 RCAR_GP_PIN(5, 24),
2732};
2733static const unsigned int msiof1_sync_f_mux[] = {
2734 MSIOF1_SYNC_F_MARK,
2735};
2736static const unsigned int msiof1_ss1_f_pins[] = {
2737 /* SS1 */
2738 RCAR_GP_PIN(6, 1),
2739};
2740static const unsigned int msiof1_ss1_f_mux[] = {
2741 MSIOF1_SS1_F_MARK,
2742};
2743static const unsigned int msiof1_ss2_f_pins[] = {
2744 /* SS2 */
2745 RCAR_GP_PIN(6, 2),
2746};
2747static const unsigned int msiof1_ss2_f_mux[] = {
2748 MSIOF1_SS2_F_MARK,
2749};
2750static const unsigned int msiof1_txd_f_pins[] = {
2751 /* TXD */
2752 RCAR_GP_PIN(6, 0),
2753};
2754static const unsigned int msiof1_txd_f_mux[] = {
2755 MSIOF1_TXD_F_MARK,
2756};
2757static const unsigned int msiof1_rxd_f_pins[] = {
2758 /* RXD */
2759 RCAR_GP_PIN(5, 25),
2760};
2761static const unsigned int msiof1_rxd_f_mux[] = {
2762 MSIOF1_RXD_F_MARK,
2763};
2764static const unsigned int msiof1_clk_g_pins[] = {
2765 /* SCK */
2766 RCAR_GP_PIN(3, 6),
2767};
2768static const unsigned int msiof1_clk_g_mux[] = {
2769 MSIOF1_SCK_G_MARK,
2770};
2771static const unsigned int msiof1_sync_g_pins[] = {
2772 /* SYNC */
2773 RCAR_GP_PIN(3, 7),
2774};
2775static const unsigned int msiof1_sync_g_mux[] = {
2776 MSIOF1_SYNC_G_MARK,
2777};
2778static const unsigned int msiof1_ss1_g_pins[] = {
2779 /* SS1 */
2780 RCAR_GP_PIN(3, 10),
2781};
2782static const unsigned int msiof1_ss1_g_mux[] = {
2783 MSIOF1_SS1_G_MARK,
2784};
2785static const unsigned int msiof1_ss2_g_pins[] = {
2786 /* SS2 */
2787 RCAR_GP_PIN(3, 11),
2788};
2789static const unsigned int msiof1_ss2_g_mux[] = {
2790 MSIOF1_SS2_G_MARK,
2791};
2792static const unsigned int msiof1_txd_g_pins[] = {
2793 /* TXD */
2794 RCAR_GP_PIN(3, 9),
2795};
2796static const unsigned int msiof1_txd_g_mux[] = {
2797 MSIOF1_TXD_G_MARK,
2798};
2799static const unsigned int msiof1_rxd_g_pins[] = {
2800 /* RXD */
2801 RCAR_GP_PIN(3, 8),
2802};
2803static const unsigned int msiof1_rxd_g_mux[] = {
2804 MSIOF1_RXD_G_MARK,
2805};
2806/* - MSIOF2 ----------------------------------------------------------------- */
2807static const unsigned int msiof2_clk_a_pins[] = {
2808 /* SCK */
2809 RCAR_GP_PIN(1, 9),
2810};
2811static const unsigned int msiof2_clk_a_mux[] = {
2812 MSIOF2_SCK_A_MARK,
2813};
2814static const unsigned int msiof2_sync_a_pins[] = {
2815 /* SYNC */
2816 RCAR_GP_PIN(1, 8),
2817};
2818static const unsigned int msiof2_sync_a_mux[] = {
2819 MSIOF2_SYNC_A_MARK,
2820};
2821static const unsigned int msiof2_ss1_a_pins[] = {
2822 /* SS1 */
2823 RCAR_GP_PIN(1, 6),
2824};
2825static const unsigned int msiof2_ss1_a_mux[] = {
2826 MSIOF2_SS1_A_MARK,
2827};
2828static const unsigned int msiof2_ss2_a_pins[] = {
2829 /* SS2 */
2830 RCAR_GP_PIN(1, 7),
2831};
2832static const unsigned int msiof2_ss2_a_mux[] = {
2833 MSIOF2_SS2_A_MARK,
2834};
2835static const unsigned int msiof2_txd_a_pins[] = {
2836 /* TXD */
2837 RCAR_GP_PIN(1, 11),
2838};
2839static const unsigned int msiof2_txd_a_mux[] = {
2840 MSIOF2_TXD_A_MARK,
2841};
2842static const unsigned int msiof2_rxd_a_pins[] = {
2843 /* RXD */
2844 RCAR_GP_PIN(1, 10),
2845};
2846static const unsigned int msiof2_rxd_a_mux[] = {
2847 MSIOF2_RXD_A_MARK,
2848};
2849static const unsigned int msiof2_clk_b_pins[] = {
2850 /* SCK */
2851 RCAR_GP_PIN(0, 4),
2852};
2853static const unsigned int msiof2_clk_b_mux[] = {
2854 MSIOF2_SCK_B_MARK,
2855};
2856static const unsigned int msiof2_sync_b_pins[] = {
2857 /* SYNC */
2858 RCAR_GP_PIN(0, 5),
2859};
2860static const unsigned int msiof2_sync_b_mux[] = {
2861 MSIOF2_SYNC_B_MARK,
2862};
2863static const unsigned int msiof2_ss1_b_pins[] = {
2864 /* SS1 */
2865 RCAR_GP_PIN(0, 0),
2866};
2867static const unsigned int msiof2_ss1_b_mux[] = {
2868 MSIOF2_SS1_B_MARK,
2869};
2870static const unsigned int msiof2_ss2_b_pins[] = {
2871 /* SS2 */
2872 RCAR_GP_PIN(0, 1),
2873};
2874static const unsigned int msiof2_ss2_b_mux[] = {
2875 MSIOF2_SS2_B_MARK,
2876};
2877static const unsigned int msiof2_txd_b_pins[] = {
2878 /* TXD */
2879 RCAR_GP_PIN(0, 7),
2880};
2881static const unsigned int msiof2_txd_b_mux[] = {
2882 MSIOF2_TXD_B_MARK,
2883};
2884static const unsigned int msiof2_rxd_b_pins[] = {
2885 /* RXD */
2886 RCAR_GP_PIN(0, 6),
2887};
2888static const unsigned int msiof2_rxd_b_mux[] = {
2889 MSIOF2_RXD_B_MARK,
2890};
2891static const unsigned int msiof2_clk_c_pins[] = {
2892 /* SCK */
2893 RCAR_GP_PIN(2, 12),
2894};
2895static const unsigned int msiof2_clk_c_mux[] = {
2896 MSIOF2_SCK_C_MARK,
2897};
2898static const unsigned int msiof2_sync_c_pins[] = {
2899 /* SYNC */
2900 RCAR_GP_PIN(2, 11),
2901};
2902static const unsigned int msiof2_sync_c_mux[] = {
2903 MSIOF2_SYNC_C_MARK,
2904};
2905static const unsigned int msiof2_ss1_c_pins[] = {
2906 /* SS1 */
2907 RCAR_GP_PIN(2, 10),
2908};
2909static const unsigned int msiof2_ss1_c_mux[] = {
2910 MSIOF2_SS1_C_MARK,
2911};
2912static const unsigned int msiof2_ss2_c_pins[] = {
2913 /* SS2 */
2914 RCAR_GP_PIN(2, 9),
2915};
2916static const unsigned int msiof2_ss2_c_mux[] = {
2917 MSIOF2_SS2_C_MARK,
2918};
2919static const unsigned int msiof2_txd_c_pins[] = {
2920 /* TXD */
2921 RCAR_GP_PIN(2, 14),
2922};
2923static const unsigned int msiof2_txd_c_mux[] = {
2924 MSIOF2_TXD_C_MARK,
2925};
2926static const unsigned int msiof2_rxd_c_pins[] = {
2927 /* RXD */
2928 RCAR_GP_PIN(2, 13),
2929};
2930static const unsigned int msiof2_rxd_c_mux[] = {
2931 MSIOF2_RXD_C_MARK,
2932};
2933static const unsigned int msiof2_clk_d_pins[] = {
2934 /* SCK */
2935 RCAR_GP_PIN(0, 8),
2936};
2937static const unsigned int msiof2_clk_d_mux[] = {
2938 MSIOF2_SCK_D_MARK,
2939};
2940static const unsigned int msiof2_sync_d_pins[] = {
2941 /* SYNC */
2942 RCAR_GP_PIN(0, 9),
2943};
2944static const unsigned int msiof2_sync_d_mux[] = {
2945 MSIOF2_SYNC_D_MARK,
2946};
2947static const unsigned int msiof2_ss1_d_pins[] = {
2948 /* SS1 */
2949 RCAR_GP_PIN(0, 12),
2950};
2951static const unsigned int msiof2_ss1_d_mux[] = {
2952 MSIOF2_SS1_D_MARK,
2953};
2954static const unsigned int msiof2_ss2_d_pins[] = {
2955 /* SS2 */
2956 RCAR_GP_PIN(0, 13),
2957};
2958static const unsigned int msiof2_ss2_d_mux[] = {
2959 MSIOF2_SS2_D_MARK,
2960};
2961static const unsigned int msiof2_txd_d_pins[] = {
2962 /* TXD */
2963 RCAR_GP_PIN(0, 11),
2964};
2965static const unsigned int msiof2_txd_d_mux[] = {
2966 MSIOF2_TXD_D_MARK,
2967};
2968static const unsigned int msiof2_rxd_d_pins[] = {
2969 /* RXD */
2970 RCAR_GP_PIN(0, 10),
2971};
2972static const unsigned int msiof2_rxd_d_mux[] = {
2973 MSIOF2_RXD_D_MARK,
2974};
2975/* - MSIOF3 ----------------------------------------------------------------- */
2976static const unsigned int msiof3_clk_a_pins[] = {
2977 /* SCK */
2978 RCAR_GP_PIN(0, 0),
2979};
2980static const unsigned int msiof3_clk_a_mux[] = {
2981 MSIOF3_SCK_A_MARK,
2982};
2983static const unsigned int msiof3_sync_a_pins[] = {
2984 /* SYNC */
2985 RCAR_GP_PIN(0, 1),
2986};
2987static const unsigned int msiof3_sync_a_mux[] = {
2988 MSIOF3_SYNC_A_MARK,
2989};
2990static const unsigned int msiof3_ss1_a_pins[] = {
2991 /* SS1 */
2992 RCAR_GP_PIN(0, 14),
2993};
2994static const unsigned int msiof3_ss1_a_mux[] = {
2995 MSIOF3_SS1_A_MARK,
2996};
2997static const unsigned int msiof3_ss2_a_pins[] = {
2998 /* SS2 */
2999 RCAR_GP_PIN(0, 15),
3000};
3001static const unsigned int msiof3_ss2_a_mux[] = {
3002 MSIOF3_SS2_A_MARK,
3003};
3004static const unsigned int msiof3_txd_a_pins[] = {
3005 /* TXD */
3006 RCAR_GP_PIN(0, 3),
3007};
3008static const unsigned int msiof3_txd_a_mux[] = {
3009 MSIOF3_TXD_A_MARK,
3010};
3011static const unsigned int msiof3_rxd_a_pins[] = {
3012 /* RXD */
3013 RCAR_GP_PIN(0, 2),
3014};
3015static const unsigned int msiof3_rxd_a_mux[] = {
3016 MSIOF3_RXD_A_MARK,
3017};
3018static const unsigned int msiof3_clk_b_pins[] = {
3019 /* SCK */
3020 RCAR_GP_PIN(1, 2),
3021};
3022static const unsigned int msiof3_clk_b_mux[] = {
3023 MSIOF3_SCK_B_MARK,
3024};
3025static const unsigned int msiof3_sync_b_pins[] = {
3026 /* SYNC */
3027 RCAR_GP_PIN(1, 0),
3028};
3029static const unsigned int msiof3_sync_b_mux[] = {
3030 MSIOF3_SYNC_B_MARK,
3031};
3032static const unsigned int msiof3_ss1_b_pins[] = {
3033 /* SS1 */
3034 RCAR_GP_PIN(1, 4),
3035};
3036static const unsigned int msiof3_ss1_b_mux[] = {
3037 MSIOF3_SS1_B_MARK,
3038};
3039static const unsigned int msiof3_ss2_b_pins[] = {
3040 /* SS2 */
3041 RCAR_GP_PIN(1, 5),
3042};
3043static const unsigned int msiof3_ss2_b_mux[] = {
3044 MSIOF3_SS2_B_MARK,
3045};
3046static const unsigned int msiof3_txd_b_pins[] = {
3047 /* TXD */
3048 RCAR_GP_PIN(1, 1),
3049};
3050static const unsigned int msiof3_txd_b_mux[] = {
3051 MSIOF3_TXD_B_MARK,
3052};
3053static const unsigned int msiof3_rxd_b_pins[] = {
3054 /* RXD */
3055 RCAR_GP_PIN(1, 3),
3056};
3057static const unsigned int msiof3_rxd_b_mux[] = {
3058 MSIOF3_RXD_B_MARK,
3059};
3060static const unsigned int msiof3_clk_c_pins[] = {
3061 /* SCK */
3062 RCAR_GP_PIN(1, 12),
3063};
3064static const unsigned int msiof3_clk_c_mux[] = {
3065 MSIOF3_SCK_C_MARK,
3066};
3067static const unsigned int msiof3_sync_c_pins[] = {
3068 /* SYNC */
3069 RCAR_GP_PIN(1, 13),
3070};
3071static const unsigned int msiof3_sync_c_mux[] = {
3072 MSIOF3_SYNC_C_MARK,
3073};
3074static const unsigned int msiof3_txd_c_pins[] = {
3075 /* TXD */
3076 RCAR_GP_PIN(1, 15),
3077};
3078static const unsigned int msiof3_txd_c_mux[] = {
3079 MSIOF3_TXD_C_MARK,
3080};
3081static const unsigned int msiof3_rxd_c_pins[] = {
3082 /* RXD */
3083 RCAR_GP_PIN(1, 14),
3084};
3085static const unsigned int msiof3_rxd_c_mux[] = {
3086 MSIOF3_RXD_C_MARK,
3087};
3088static const unsigned int msiof3_clk_d_pins[] = {
3089 /* SCK */
3090 RCAR_GP_PIN(1, 22),
3091};
3092static const unsigned int msiof3_clk_d_mux[] = {
3093 MSIOF3_SCK_D_MARK,
3094};
3095static const unsigned int msiof3_sync_d_pins[] = {
3096 /* SYNC */
3097 RCAR_GP_PIN(1, 23),
3098};
3099static const unsigned int msiof3_sync_d_mux[] = {
3100 MSIOF3_SYNC_D_MARK,
3101};
3102static const unsigned int msiof3_ss1_d_pins[] = {
3103 /* SS1 */
3104 RCAR_GP_PIN(1, 26),
3105};
3106static const unsigned int msiof3_ss1_d_mux[] = {
3107 MSIOF3_SS1_D_MARK,
3108};
3109static const unsigned int msiof3_txd_d_pins[] = {
3110 /* TXD */
3111 RCAR_GP_PIN(1, 25),
3112};
3113static const unsigned int msiof3_txd_d_mux[] = {
3114 MSIOF3_TXD_D_MARK,
3115};
3116static const unsigned int msiof3_rxd_d_pins[] = {
3117 /* RXD */
3118 RCAR_GP_PIN(1, 24),
3119};
3120static const unsigned int msiof3_rxd_d_mux[] = {
3121 MSIOF3_RXD_D_MARK,
3122};
3123static const unsigned int msiof3_clk_e_pins[] = {
3124 /* SCK */
3125 RCAR_GP_PIN(2, 3),
3126};
3127static const unsigned int msiof3_clk_e_mux[] = {
3128 MSIOF3_SCK_E_MARK,
3129};
3130static const unsigned int msiof3_sync_e_pins[] = {
3131 /* SYNC */
3132 RCAR_GP_PIN(2, 2),
3133};
3134static const unsigned int msiof3_sync_e_mux[] = {
3135 MSIOF3_SYNC_E_MARK,
3136};
3137static const unsigned int msiof3_ss1_e_pins[] = {
3138 /* SS1 */
3139 RCAR_GP_PIN(2, 1),
3140};
3141static const unsigned int msiof3_ss1_e_mux[] = {
3142 MSIOF3_SS1_E_MARK,
3143};
3144static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3145 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3146 RCAR_GP_PIN(2, 0),
3147};
3148static const unsigned int msiof3_ss2_e_mux[] = {
3149 MSIOF3_SS2_E_MARK,
3150};
3151static const unsigned int msiof3_txd_e_pins[] = {
3152 /* TXD */
3153 RCAR_GP_PIN(2, 5),
3154};
3155static const unsigned int msiof3_txd_e_mux[] = {
3156 MSIOF3_TXD_E_MARK,
3157};
3158static const unsigned int msiof3_rxd_e_pins[] = {
3159 /* RXD */
3160 RCAR_GP_PIN(2, 4),
3161};
3162static const unsigned int msiof3_rxd_e_mux[] = {
3163 MSIOF3_RXD_E_MARK,
3164};
3165
3166/* - PWM0 --------------------------------------------------------------------*/
3167static const unsigned int pwm0_pins[] = {
3168 /* PWM */
3169 RCAR_GP_PIN(2, 6),
3170};
3171static const unsigned int pwm0_mux[] = {
3172 PWM0_MARK,
3173};
3174/* - PWM1 --------------------------------------------------------------------*/
3175static const unsigned int pwm1_a_pins[] = {
3176 /* PWM */
3177 RCAR_GP_PIN(2, 7),
3178};
3179static const unsigned int pwm1_a_mux[] = {
3180 PWM1_A_MARK,
3181};
3182static const unsigned int pwm1_b_pins[] = {
3183 /* PWM */
3184 RCAR_GP_PIN(1, 8),
3185};
3186static const unsigned int pwm1_b_mux[] = {
3187 PWM1_B_MARK,
3188};
3189/* - PWM2 --------------------------------------------------------------------*/
3190static const unsigned int pwm2_a_pins[] = {
3191 /* PWM */
3192 RCAR_GP_PIN(2, 8),
3193};
3194static const unsigned int pwm2_a_mux[] = {
3195 PWM2_A_MARK,
3196};
3197static const unsigned int pwm2_b_pins[] = {
3198 /* PWM */
3199 RCAR_GP_PIN(1, 11),
3200};
3201static const unsigned int pwm2_b_mux[] = {
3202 PWM2_B_MARK,
3203};
3204/* - PWM3 --------------------------------------------------------------------*/
3205static const unsigned int pwm3_a_pins[] = {
3206 /* PWM */
3207 RCAR_GP_PIN(1, 0),
3208};
3209static const unsigned int pwm3_a_mux[] = {
3210 PWM3_A_MARK,
3211};
3212static const unsigned int pwm3_b_pins[] = {
3213 /* PWM */
3214 RCAR_GP_PIN(2, 2),
3215};
3216static const unsigned int pwm3_b_mux[] = {
3217 PWM3_B_MARK,
3218};
3219/* - PWM4 --------------------------------------------------------------------*/
3220static const unsigned int pwm4_a_pins[] = {
3221 /* PWM */
3222 RCAR_GP_PIN(1, 1),
3223};
3224static const unsigned int pwm4_a_mux[] = {
3225 PWM4_A_MARK,
3226};
3227static const unsigned int pwm4_b_pins[] = {
3228 /* PWM */
3229 RCAR_GP_PIN(2, 3),
3230};
3231static const unsigned int pwm4_b_mux[] = {
3232 PWM4_B_MARK,
3233};
3234/* - PWM5 --------------------------------------------------------------------*/
3235static const unsigned int pwm5_a_pins[] = {
3236 /* PWM */
3237 RCAR_GP_PIN(1, 2),
3238};
3239static const unsigned int pwm5_a_mux[] = {
3240 PWM5_A_MARK,
3241};
3242static const unsigned int pwm5_b_pins[] = {
3243 /* PWM */
3244 RCAR_GP_PIN(2, 4),
3245};
3246static const unsigned int pwm5_b_mux[] = {
3247 PWM5_B_MARK,
3248};
3249/* - PWM6 --------------------------------------------------------------------*/
3250static const unsigned int pwm6_a_pins[] = {
3251 /* PWM */
3252 RCAR_GP_PIN(1, 3),
3253};
3254static const unsigned int pwm6_a_mux[] = {
3255 PWM6_A_MARK,
3256};
3257static const unsigned int pwm6_b_pins[] = {
3258 /* PWM */
3259 RCAR_GP_PIN(2, 5),
3260};
3261static const unsigned int pwm6_b_mux[] = {
3262 PWM6_B_MARK,
3263};
3264
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3265/* - QSPI0 ------------------------------------------------------------------ */
3266static const unsigned int qspi0_ctrl_pins[] = {
3267 /* QSPI0_SPCLK, QSPI0_SSL */
3268 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3269};
3270static const unsigned int qspi0_ctrl_mux[] = {
3271 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3272};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3273static const unsigned int qspi0_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3274 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3275 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3276 /* QSPI0_IO2, QSPI0_IO3 */
3277 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3278};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3279static const unsigned int qspi0_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3280 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3281 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3282};
3283/* - QSPI1 ------------------------------------------------------------------ */
3284static const unsigned int qspi1_ctrl_pins[] = {
3285 /* QSPI1_SPCLK, QSPI1_SSL */
3286 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3287};
3288static const unsigned int qspi1_ctrl_mux[] = {
3289 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3290};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3291static const unsigned int qspi1_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3292 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3293 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3294 /* QSPI1_IO2, QSPI1_IO3 */
3295 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3296};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3297static const unsigned int qspi1_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3298 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3299 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3300};
3301
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3302/* - SATA --------------------------------------------------------------------*/
3303static const unsigned int sata0_devslp_a_pins[] = {
3304 /* DEVSLP */
3305 RCAR_GP_PIN(6, 16),
3306};
3307static const unsigned int sata0_devslp_a_mux[] = {
3308 SATA_DEVSLP_A_MARK,
3309};
3310static const unsigned int sata0_devslp_b_pins[] = {
3311 /* DEVSLP */
3312 RCAR_GP_PIN(4, 6),
3313};
3314static const unsigned int sata0_devslp_b_mux[] = {
3315 SATA_DEVSLP_B_MARK,
3316};
3317
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3318/* - SCIF0 ------------------------------------------------------------------ */
3319static const unsigned int scif0_data_pins[] = {
3320 /* RX, TX */
3321 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3322};
3323static const unsigned int scif0_data_mux[] = {
3324 RX0_MARK, TX0_MARK,
3325};
3326static const unsigned int scif0_clk_pins[] = {
3327 /* SCK */
3328 RCAR_GP_PIN(5, 0),
3329};
3330static const unsigned int scif0_clk_mux[] = {
3331 SCK0_MARK,
3332};
3333static const unsigned int scif0_ctrl_pins[] = {
3334 /* RTS, CTS */
3335 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3336};
3337static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3338 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3339};
3340/* - SCIF1 ------------------------------------------------------------------ */
3341static const unsigned int scif1_data_a_pins[] = {
3342 /* RX, TX */
3343 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3344};
3345static const unsigned int scif1_data_a_mux[] = {
3346 RX1_A_MARK, TX1_A_MARK,
3347};
3348static const unsigned int scif1_clk_pins[] = {
3349 /* SCK */
3350 RCAR_GP_PIN(6, 21),
3351};
3352static const unsigned int scif1_clk_mux[] = {
3353 SCK1_MARK,
3354};
3355static const unsigned int scif1_ctrl_pins[] = {
3356 /* RTS, CTS */
3357 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3358};
3359static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3360 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3361};
3362
3363static const unsigned int scif1_data_b_pins[] = {
3364 /* RX, TX */
3365 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3366};
3367static const unsigned int scif1_data_b_mux[] = {
3368 RX1_B_MARK, TX1_B_MARK,
3369};
3370/* - SCIF2 ------------------------------------------------------------------ */
3371static const unsigned int scif2_data_a_pins[] = {
3372 /* RX, TX */
3373 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3374};
3375static const unsigned int scif2_data_a_mux[] = {
3376 RX2_A_MARK, TX2_A_MARK,
3377};
3378static const unsigned int scif2_clk_pins[] = {
3379 /* SCK */
3380 RCAR_GP_PIN(5, 9),
3381};
3382static const unsigned int scif2_clk_mux[] = {
3383 SCK2_MARK,
3384};
3385static const unsigned int scif2_data_b_pins[] = {
3386 /* RX, TX */
3387 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3388};
3389static const unsigned int scif2_data_b_mux[] = {
3390 RX2_B_MARK, TX2_B_MARK,
3391};
3392/* - SCIF3 ------------------------------------------------------------------ */
3393static const unsigned int scif3_data_a_pins[] = {
3394 /* RX, TX */
3395 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3396};
3397static const unsigned int scif3_data_a_mux[] = {
3398 RX3_A_MARK, TX3_A_MARK,
3399};
3400static const unsigned int scif3_clk_pins[] = {
3401 /* SCK */
3402 RCAR_GP_PIN(1, 22),
3403};
3404static const unsigned int scif3_clk_mux[] = {
3405 SCK3_MARK,
3406};
3407static const unsigned int scif3_ctrl_pins[] = {
3408 /* RTS, CTS */
3409 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3410};
3411static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3412 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3413};
3414static const unsigned int scif3_data_b_pins[] = {
3415 /* RX, TX */
3416 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3417};
3418static const unsigned int scif3_data_b_mux[] = {
3419 RX3_B_MARK, TX3_B_MARK,
3420};
3421/* - SCIF4 ------------------------------------------------------------------ */
3422static const unsigned int scif4_data_a_pins[] = {
3423 /* RX, TX */
3424 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3425};
3426static const unsigned int scif4_data_a_mux[] = {
3427 RX4_A_MARK, TX4_A_MARK,
3428};
3429static const unsigned int scif4_clk_a_pins[] = {
3430 /* SCK */
3431 RCAR_GP_PIN(2, 10),
3432};
3433static const unsigned int scif4_clk_a_mux[] = {
3434 SCK4_A_MARK,
3435};
3436static const unsigned int scif4_ctrl_a_pins[] = {
3437 /* RTS, CTS */
3438 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3439};
3440static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3441 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3442};
3443static const unsigned int scif4_data_b_pins[] = {
3444 /* RX, TX */
3445 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3446};
3447static const unsigned int scif4_data_b_mux[] = {
3448 RX4_B_MARK, TX4_B_MARK,
3449};
3450static const unsigned int scif4_clk_b_pins[] = {
3451 /* SCK */
3452 RCAR_GP_PIN(1, 5),
3453};
3454static const unsigned int scif4_clk_b_mux[] = {
3455 SCK4_B_MARK,
3456};
3457static const unsigned int scif4_ctrl_b_pins[] = {
3458 /* RTS, CTS */
3459 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3460};
3461static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3462 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3463};
3464static const unsigned int scif4_data_c_pins[] = {
3465 /* RX, TX */
3466 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3467};
3468static const unsigned int scif4_data_c_mux[] = {
3469 RX4_C_MARK, TX4_C_MARK,
3470};
3471static const unsigned int scif4_clk_c_pins[] = {
3472 /* SCK */
3473 RCAR_GP_PIN(0, 8),
3474};
3475static const unsigned int scif4_clk_c_mux[] = {
3476 SCK4_C_MARK,
3477};
3478static const unsigned int scif4_ctrl_c_pins[] = {
3479 /* RTS, CTS */
3480 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3481};
3482static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3483 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3484};
3485/* - SCIF5 ------------------------------------------------------------------ */
3486static const unsigned int scif5_data_a_pins[] = {
3487 /* RX, TX */
3488 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3489};
3490static const unsigned int scif5_data_a_mux[] = {
3491 RX5_A_MARK, TX5_A_MARK,
3492};
3493static const unsigned int scif5_clk_a_pins[] = {
3494 /* SCK */
3495 RCAR_GP_PIN(6, 21),
3496};
3497static const unsigned int scif5_clk_a_mux[] = {
3498 SCK5_A_MARK,
3499};
3500static const unsigned int scif5_data_b_pins[] = {
3501 /* RX, TX */
3502 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3503};
3504static const unsigned int scif5_data_b_mux[] = {
3505 RX5_B_MARK, TX5_B_MARK,
3506};
3507static const unsigned int scif5_clk_b_pins[] = {
3508 /* SCK */
3509 RCAR_GP_PIN(5, 0),
3510};
3511static const unsigned int scif5_clk_b_mux[] = {
3512 SCK5_B_MARK,
3513};
3514
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3515/* - SCIF Clock ------------------------------------------------------------- */
3516static const unsigned int scif_clk_a_pins[] = {
3517 /* SCIF_CLK */
3518 RCAR_GP_PIN(6, 23),
3519};
3520static const unsigned int scif_clk_a_mux[] = {
3521 SCIF_CLK_A_MARK,
3522};
3523static const unsigned int scif_clk_b_pins[] = {
3524 /* SCIF_CLK */
3525 RCAR_GP_PIN(5, 9),
3526};
3527static const unsigned int scif_clk_b_mux[] = {
3528 SCIF_CLK_B_MARK,
3529};
3530
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3531/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3532static const unsigned int sdhi0_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3533 /* D[0:3] */
3534 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3535 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3536};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3537static const unsigned int sdhi0_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3538 SD0_DAT0_MARK, SD0_DAT1_MARK,
3539 SD0_DAT2_MARK, SD0_DAT3_MARK,
3540};
3541static const unsigned int sdhi0_ctrl_pins[] = {
3542 /* CLK, CMD */
3543 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3544};
3545static const unsigned int sdhi0_ctrl_mux[] = {
3546 SD0_CLK_MARK, SD0_CMD_MARK,
3547};
3548static const unsigned int sdhi0_cd_pins[] = {
3549 /* CD */
3550 RCAR_GP_PIN(3, 12),
3551};
3552static const unsigned int sdhi0_cd_mux[] = {
3553 SD0_CD_MARK,
3554};
3555static const unsigned int sdhi0_wp_pins[] = {
3556 /* WP */
3557 RCAR_GP_PIN(3, 13),
3558};
3559static const unsigned int sdhi0_wp_mux[] = {
3560 SD0_WP_MARK,
3561};
3562/* - SDHI1 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3563static const unsigned int sdhi1_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3564 /* D[0:3] */
3565 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3566 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3567};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3568static const unsigned int sdhi1_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3569 SD1_DAT0_MARK, SD1_DAT1_MARK,
3570 SD1_DAT2_MARK, SD1_DAT3_MARK,
3571};
3572static const unsigned int sdhi1_ctrl_pins[] = {
3573 /* CLK, CMD */
3574 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3575};
3576static const unsigned int sdhi1_ctrl_mux[] = {
3577 SD1_CLK_MARK, SD1_CMD_MARK,
3578};
3579static const unsigned int sdhi1_cd_pins[] = {
3580 /* CD */
3581 RCAR_GP_PIN(3, 14),
3582};
3583static const unsigned int sdhi1_cd_mux[] = {
3584 SD1_CD_MARK,
3585};
3586static const unsigned int sdhi1_wp_pins[] = {
3587 /* WP */
3588 RCAR_GP_PIN(3, 15),
3589};
3590static const unsigned int sdhi1_wp_mux[] = {
3591 SD1_WP_MARK,
3592};
3593/* - SDHI2 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3594static const unsigned int sdhi2_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3595 /* D[0:7] */
3596 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3597 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3598 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3599 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3600};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3601static const unsigned int sdhi2_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3602 SD2_DAT0_MARK, SD2_DAT1_MARK,
3603 SD2_DAT2_MARK, SD2_DAT3_MARK,
3604 SD2_DAT4_MARK, SD2_DAT5_MARK,
3605 SD2_DAT6_MARK, SD2_DAT7_MARK,
3606};
3607static const unsigned int sdhi2_ctrl_pins[] = {
3608 /* CLK, CMD */
3609 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3610};
3611static const unsigned int sdhi2_ctrl_mux[] = {
3612 SD2_CLK_MARK, SD2_CMD_MARK,
3613};
3614static const unsigned int sdhi2_cd_a_pins[] = {
3615 /* CD */
3616 RCAR_GP_PIN(4, 13),
3617};
3618static const unsigned int sdhi2_cd_a_mux[] = {
3619 SD2_CD_A_MARK,
3620};
3621static const unsigned int sdhi2_cd_b_pins[] = {
3622 /* CD */
3623 RCAR_GP_PIN(5, 10),
3624};
3625static const unsigned int sdhi2_cd_b_mux[] = {
3626 SD2_CD_B_MARK,
3627};
3628static const unsigned int sdhi2_wp_a_pins[] = {
3629 /* WP */
3630 RCAR_GP_PIN(4, 14),
3631};
3632static const unsigned int sdhi2_wp_a_mux[] = {
3633 SD2_WP_A_MARK,
3634};
3635static const unsigned int sdhi2_wp_b_pins[] = {
3636 /* WP */
3637 RCAR_GP_PIN(5, 11),
3638};
3639static const unsigned int sdhi2_wp_b_mux[] = {
3640 SD2_WP_B_MARK,
3641};
3642static const unsigned int sdhi2_ds_pins[] = {
3643 /* DS */
3644 RCAR_GP_PIN(4, 6),
3645};
3646static const unsigned int sdhi2_ds_mux[] = {
3647 SD2_DS_MARK,
3648};
3649/* - SDHI3 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3650static const unsigned int sdhi3_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3651 /* D[0:7] */
3652 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3653 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3654 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3655 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3656};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3657static const unsigned int sdhi3_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3658 SD3_DAT0_MARK, SD3_DAT1_MARK,
3659 SD3_DAT2_MARK, SD3_DAT3_MARK,
3660 SD3_DAT4_MARK, SD3_DAT5_MARK,
3661 SD3_DAT6_MARK, SD3_DAT7_MARK,
3662};
3663static const unsigned int sdhi3_ctrl_pins[] = {
3664 /* CLK, CMD */
3665 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3666};
3667static const unsigned int sdhi3_ctrl_mux[] = {
3668 SD3_CLK_MARK, SD3_CMD_MARK,
3669};
3670static const unsigned int sdhi3_cd_pins[] = {
3671 /* CD */
3672 RCAR_GP_PIN(4, 15),
3673};
3674static const unsigned int sdhi3_cd_mux[] = {
3675 SD3_CD_MARK,
3676};
3677static const unsigned int sdhi3_wp_pins[] = {
3678 /* WP */
3679 RCAR_GP_PIN(4, 16),
3680};
3681static const unsigned int sdhi3_wp_mux[] = {
3682 SD3_WP_MARK,
3683};
3684static const unsigned int sdhi3_ds_pins[] = {
3685 /* DS */
3686 RCAR_GP_PIN(4, 17),
3687};
3688static const unsigned int sdhi3_ds_mux[] = {
3689 SD3_DS_MARK,
3690};
3691
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3692/* - SSI -------------------------------------------------------------------- */
3693static const unsigned int ssi0_data_pins[] = {
3694 /* SDATA */
3695 RCAR_GP_PIN(6, 2),
3696};
3697static const unsigned int ssi0_data_mux[] = {
3698 SSI_SDATA0_MARK,
3699};
3700static const unsigned int ssi01239_ctrl_pins[] = {
3701 /* SCK, WS */
3702 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3703};
3704static const unsigned int ssi01239_ctrl_mux[] = {
3705 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3706};
3707static const unsigned int ssi1_data_a_pins[] = {
3708 /* SDATA */
3709 RCAR_GP_PIN(6, 3),
3710};
3711static const unsigned int ssi1_data_a_mux[] = {
3712 SSI_SDATA1_A_MARK,
3713};
3714static const unsigned int ssi1_data_b_pins[] = {
3715 /* SDATA */
3716 RCAR_GP_PIN(5, 12),
3717};
3718static const unsigned int ssi1_data_b_mux[] = {
3719 SSI_SDATA1_B_MARK,
3720};
3721static const unsigned int ssi1_ctrl_a_pins[] = {
3722 /* SCK, WS */
3723 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3724};
3725static const unsigned int ssi1_ctrl_a_mux[] = {
3726 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3727};
3728static const unsigned int ssi1_ctrl_b_pins[] = {
3729 /* SCK, WS */
3730 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3731};
3732static const unsigned int ssi1_ctrl_b_mux[] = {
3733 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3734};
3735static const unsigned int ssi2_data_a_pins[] = {
3736 /* SDATA */
3737 RCAR_GP_PIN(6, 4),
3738};
3739static const unsigned int ssi2_data_a_mux[] = {
3740 SSI_SDATA2_A_MARK,
3741};
3742static const unsigned int ssi2_data_b_pins[] = {
3743 /* SDATA */
3744 RCAR_GP_PIN(5, 13),
3745};
3746static const unsigned int ssi2_data_b_mux[] = {
3747 SSI_SDATA2_B_MARK,
3748};
3749static const unsigned int ssi2_ctrl_a_pins[] = {
3750 /* SCK, WS */
3751 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3752};
3753static const unsigned int ssi2_ctrl_a_mux[] = {
3754 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3755};
3756static const unsigned int ssi2_ctrl_b_pins[] = {
3757 /* SCK, WS */
3758 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3759};
3760static const unsigned int ssi2_ctrl_b_mux[] = {
3761 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3762};
3763static const unsigned int ssi3_data_pins[] = {
3764 /* SDATA */
3765 RCAR_GP_PIN(6, 7),
3766};
3767static const unsigned int ssi3_data_mux[] = {
3768 SSI_SDATA3_MARK,
3769};
3770static const unsigned int ssi349_ctrl_pins[] = {
3771 /* SCK, WS */
3772 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3773};
3774static const unsigned int ssi349_ctrl_mux[] = {
3775 SSI_SCK349_MARK, SSI_WS349_MARK,
3776};
3777static const unsigned int ssi4_data_pins[] = {
3778 /* SDATA */
3779 RCAR_GP_PIN(6, 10),
3780};
3781static const unsigned int ssi4_data_mux[] = {
3782 SSI_SDATA4_MARK,
3783};
3784static const unsigned int ssi4_ctrl_pins[] = {
3785 /* SCK, WS */
3786 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3787};
3788static const unsigned int ssi4_ctrl_mux[] = {
3789 SSI_SCK4_MARK, SSI_WS4_MARK,
3790};
3791static const unsigned int ssi5_data_pins[] = {
3792 /* SDATA */
3793 RCAR_GP_PIN(6, 13),
3794};
3795static const unsigned int ssi5_data_mux[] = {
3796 SSI_SDATA5_MARK,
3797};
3798static const unsigned int ssi5_ctrl_pins[] = {
3799 /* SCK, WS */
3800 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3801};
3802static const unsigned int ssi5_ctrl_mux[] = {
3803 SSI_SCK5_MARK, SSI_WS5_MARK,
3804};
3805static const unsigned int ssi6_data_pins[] = {
3806 /* SDATA */
3807 RCAR_GP_PIN(6, 16),
3808};
3809static const unsigned int ssi6_data_mux[] = {
3810 SSI_SDATA6_MARK,
3811};
3812static const unsigned int ssi6_ctrl_pins[] = {
3813 /* SCK, WS */
3814 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3815};
3816static const unsigned int ssi6_ctrl_mux[] = {
3817 SSI_SCK6_MARK, SSI_WS6_MARK,
3818};
3819static const unsigned int ssi7_data_pins[] = {
3820 /* SDATA */
3821 RCAR_GP_PIN(6, 19),
3822};
3823static const unsigned int ssi7_data_mux[] = {
3824 SSI_SDATA7_MARK,
3825};
3826static const unsigned int ssi78_ctrl_pins[] = {
3827 /* SCK, WS */
3828 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3829};
3830static const unsigned int ssi78_ctrl_mux[] = {
3831 SSI_SCK78_MARK, SSI_WS78_MARK,
3832};
3833static const unsigned int ssi8_data_pins[] = {
3834 /* SDATA */
3835 RCAR_GP_PIN(6, 20),
3836};
3837static const unsigned int ssi8_data_mux[] = {
3838 SSI_SDATA8_MARK,
3839};
3840static const unsigned int ssi9_data_a_pins[] = {
3841 /* SDATA */
3842 RCAR_GP_PIN(6, 21),
3843};
3844static const unsigned int ssi9_data_a_mux[] = {
3845 SSI_SDATA9_A_MARK,
3846};
3847static const unsigned int ssi9_data_b_pins[] = {
3848 /* SDATA */
3849 RCAR_GP_PIN(5, 14),
3850};
3851static const unsigned int ssi9_data_b_mux[] = {
3852 SSI_SDATA9_B_MARK,
3853};
3854static const unsigned int ssi9_ctrl_a_pins[] = {
3855 /* SCK, WS */
3856 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3857};
3858static const unsigned int ssi9_ctrl_a_mux[] = {
3859 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3860};
3861static const unsigned int ssi9_ctrl_b_pins[] = {
3862 /* SCK, WS */
3863 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3864};
3865static const unsigned int ssi9_ctrl_b_mux[] = {
3866 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3867};
3868
3869/* - TMU -------------------------------------------------------------------- */
3870static const unsigned int tmu_tclk1_a_pins[] = {
3871 /* TCLK */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3872 RCAR_GP_PIN(6, 23),
3873};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3874static const unsigned int tmu_tclk1_a_mux[] = {
3875 TCLK1_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3876};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3877static const unsigned int tmu_tclk1_b_pins[] = {
3878 /* TCLK */
3879 RCAR_GP_PIN(5, 19),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3880};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3881static const unsigned int tmu_tclk1_b_mux[] = {
3882 TCLK1_B_MARK,
3883};
3884static const unsigned int tmu_tclk2_a_pins[] = {
3885 /* TCLK */
3886 RCAR_GP_PIN(6, 19),
3887};
3888static const unsigned int tmu_tclk2_a_mux[] = {
3889 TCLK2_A_MARK,
3890};
3891static const unsigned int tmu_tclk2_b_pins[] = {
3892 /* TCLK */
3893 RCAR_GP_PIN(6, 28),
3894};
3895static const unsigned int tmu_tclk2_b_mux[] = {
3896 TCLK2_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3897};
3898
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]3899/* - TPU ------------------------------------------------------------------- */
3900static const unsigned int tpu_to0_pins[] = {
3901 /* TPU0TO0 */
3902 RCAR_GP_PIN(6, 28),
3903};
3904static const unsigned int tpu_to0_mux[] = {
3905 TPU0TO0_MARK,
3906};
3907static const unsigned int tpu_to1_pins[] = {
3908 /* TPU0TO1 */
3909 RCAR_GP_PIN(6, 29),
3910};
3911static const unsigned int tpu_to1_mux[] = {
3912 TPU0TO1_MARK,
3913};
3914static const unsigned int tpu_to2_pins[] = {
3915 /* TPU0TO2 */
3916 RCAR_GP_PIN(6, 30),
3917};
3918static const unsigned int tpu_to2_mux[] = {
3919 TPU0TO2_MARK,
3920};
3921static const unsigned int tpu_to3_pins[] = {
3922 /* TPU0TO3 */
3923 RCAR_GP_PIN(6, 31),
3924};
3925static const unsigned int tpu_to3_mux[] = {
3926 TPU0TO3_MARK,
3927};
3928
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3929/* - USB0 ------------------------------------------------------------------- */
3930static const unsigned int usb0_pins[] = {
3931 /* PWEN, OVC */
3932 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3933};
3934static const unsigned int usb0_mux[] = {
3935 USB0_PWEN_MARK, USB0_OVC_MARK,
3936};
3937/* - USB1 ------------------------------------------------------------------- */
3938static const unsigned int usb1_pins[] = {
3939 /* PWEN, OVC */
3940 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3941};
3942static const unsigned int usb1_mux[] = {
3943 USB1_PWEN_MARK, USB1_OVC_MARK,
3944};
3945/* - USB2 ------------------------------------------------------------------- */
3946static const unsigned int usb2_pins[] = {
3947 /* PWEN, OVC */
3948 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3949};
3950static const unsigned int usb2_mux[] = {
3951 USB2_PWEN_MARK, USB2_OVC_MARK,
3952};
3953/* - USB2_CH3 --------------------------------------------------------------- */
3954static const unsigned int usb2_ch3_pins[] = {
3955 /* PWEN, OVC */
3956 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3957};
3958static const unsigned int usb2_ch3_mux[] = {
3959 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3960};
3961
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3962/* - USB30 ------------------------------------------------------------------ */
3963static const unsigned int usb30_pins[] = {
3964 /* PWEN, OVC */
3965 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3966};
3967static const unsigned int usb30_mux[] = {
3968 USB30_PWEN_MARK, USB30_OVC_MARK,
3969};
3970
3971/* - VIN4 ------------------------------------------------------------------- */
3972static const unsigned int vin4_data18_a_pins[] = {
3973 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3974 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3975 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3976 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3977 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3978 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3979 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3980 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3981 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3982};
3983static const unsigned int vin4_data18_a_mux[] = {
3984 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3985 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3986 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3987 VI4_DATA10_MARK, VI4_DATA11_MARK,
3988 VI4_DATA12_MARK, VI4_DATA13_MARK,
3989 VI4_DATA14_MARK, VI4_DATA15_MARK,
3990 VI4_DATA18_MARK, VI4_DATA19_MARK,
3991 VI4_DATA20_MARK, VI4_DATA21_MARK,
3992 VI4_DATA22_MARK, VI4_DATA23_MARK,
3993};
3994static const unsigned int vin4_data18_b_pins[] = {
3995 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3996 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3997 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3998 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3999 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4000 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4001 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4002 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4003 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4004};
4005static const unsigned int vin4_data18_b_mux[] = {
4006 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4007 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4008 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4009 VI4_DATA10_MARK, VI4_DATA11_MARK,
4010 VI4_DATA12_MARK, VI4_DATA13_MARK,
4011 VI4_DATA14_MARK, VI4_DATA15_MARK,
4012 VI4_DATA18_MARK, VI4_DATA19_MARK,
4013 VI4_DATA20_MARK, VI4_DATA21_MARK,
4014 VI4_DATA22_MARK, VI4_DATA23_MARK,
4015};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4016static const unsigned int vin4_data_a_pins[] = {
4017 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4018 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4019 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4020 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4021 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4022 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4023 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4024 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4025 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4026 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4027 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4028 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4029};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4030static const unsigned int vin4_data_a_mux[] = {
4031 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4032 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4033 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4034 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4035 VI4_DATA8_MARK, VI4_DATA9_MARK,
4036 VI4_DATA10_MARK, VI4_DATA11_MARK,
4037 VI4_DATA12_MARK, VI4_DATA13_MARK,
4038 VI4_DATA14_MARK, VI4_DATA15_MARK,
4039 VI4_DATA16_MARK, VI4_DATA17_MARK,
4040 VI4_DATA18_MARK, VI4_DATA19_MARK,
4041 VI4_DATA20_MARK, VI4_DATA21_MARK,
4042 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4043};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4044static const unsigned int vin4_data_b_pins[] = {
4045 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4046 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4047 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4048 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4049 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4050 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4051 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4052 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4053 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4054 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4055 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4056 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4057};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4058static const unsigned int vin4_data_b_mux[] = {
4059 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4060 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4061 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4062 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4063 VI4_DATA8_MARK, VI4_DATA9_MARK,
4064 VI4_DATA10_MARK, VI4_DATA11_MARK,
4065 VI4_DATA12_MARK, VI4_DATA13_MARK,
4066 VI4_DATA14_MARK, VI4_DATA15_MARK,
4067 VI4_DATA16_MARK, VI4_DATA17_MARK,
4068 VI4_DATA18_MARK, VI4_DATA19_MARK,
4069 VI4_DATA20_MARK, VI4_DATA21_MARK,
4070 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4071};
4072static const unsigned int vin4_sync_pins[] = {
4073 /* HSYNC#, VSYNC# */
4074 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4075};
4076static const unsigned int vin4_sync_mux[] = {
4077 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4078};
4079static const unsigned int vin4_field_pins[] = {
4080 /* FIELD */
4081 RCAR_GP_PIN(1, 16),
4082};
4083static const unsigned int vin4_field_mux[] = {
4084 VI4_FIELD_MARK,
4085};
4086static const unsigned int vin4_clkenb_pins[] = {
4087 /* CLKENB */
4088 RCAR_GP_PIN(1, 19),
4089};
4090static const unsigned int vin4_clkenb_mux[] = {
4091 VI4_CLKENB_MARK,
4092};
4093static const unsigned int vin4_clk_pins[] = {
4094 /* CLK */
4095 RCAR_GP_PIN(1, 27),
4096};
4097static const unsigned int vin4_clk_mux[] = {
4098 VI4_CLK_MARK,
4099};
4100
4101/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4102static const unsigned int vin5_data_pins[] = {
4103 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4104 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4105 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4106 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4107 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4108 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4109 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4110 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4111};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4112static const unsigned int vin5_data_mux[] = {
4113 VI5_DATA0_MARK, VI5_DATA1_MARK,
4114 VI5_DATA2_MARK, VI5_DATA3_MARK,
4115 VI5_DATA4_MARK, VI5_DATA5_MARK,
4116 VI5_DATA6_MARK, VI5_DATA7_MARK,
4117 VI5_DATA8_MARK, VI5_DATA9_MARK,
4118 VI5_DATA10_MARK, VI5_DATA11_MARK,
4119 VI5_DATA12_MARK, VI5_DATA13_MARK,
4120 VI5_DATA14_MARK, VI5_DATA15_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4121};
4122static const unsigned int vin5_sync_pins[] = {
4123 /* HSYNC#, VSYNC# */
4124 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4125};
4126static const unsigned int vin5_sync_mux[] = {
4127 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4128};
4129static const unsigned int vin5_field_pins[] = {
4130 RCAR_GP_PIN(1, 11),
4131};
4132static const unsigned int vin5_field_mux[] = {
4133 /* FIELD */
4134 VI5_FIELD_MARK,
4135};
4136static const unsigned int vin5_clkenb_pins[] = {
4137 RCAR_GP_PIN(1, 20),
4138};
4139static const unsigned int vin5_clkenb_mux[] = {
4140 /* CLKENB */
4141 VI5_CLKENB_MARK,
4142};
4143static const unsigned int vin5_clk_pins[] = {
4144 RCAR_GP_PIN(1, 21),
4145};
4146static const unsigned int vin5_clk_mux[] = {
4147 /* CLK */
4148 VI5_CLK_MARK,
4149};
4150
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4151static const struct {
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4152 struct sh_pfc_pin_group common[328];
4153#ifdef CONFIG_PINCTRL_PFC_R8A77951
4154 struct sh_pfc_pin_group automotive[31];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4155#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4156} pinmux_groups = {
4157 .common = {
4158 SH_PFC_PIN_GROUP(audio_clk_a_a),
4159 SH_PFC_PIN_GROUP(audio_clk_a_b),
4160 SH_PFC_PIN_GROUP(audio_clk_a_c),
4161 SH_PFC_PIN_GROUP(audio_clk_b_a),
4162 SH_PFC_PIN_GROUP(audio_clk_b_b),
4163 SH_PFC_PIN_GROUP(audio_clk_c_a),
4164 SH_PFC_PIN_GROUP(audio_clk_c_b),
4165 SH_PFC_PIN_GROUP(audio_clkout_a),
4166 SH_PFC_PIN_GROUP(audio_clkout_b),
4167 SH_PFC_PIN_GROUP(audio_clkout_c),
4168 SH_PFC_PIN_GROUP(audio_clkout_d),
4169 SH_PFC_PIN_GROUP(audio_clkout1_a),
4170 SH_PFC_PIN_GROUP(audio_clkout1_b),
4171 SH_PFC_PIN_GROUP(audio_clkout2_a),
4172 SH_PFC_PIN_GROUP(audio_clkout2_b),
4173 SH_PFC_PIN_GROUP(audio_clkout3_a),
4174 SH_PFC_PIN_GROUP(audio_clkout3_b),
4175 SH_PFC_PIN_GROUP(avb_link),
4176 SH_PFC_PIN_GROUP(avb_magic),
4177 SH_PFC_PIN_GROUP(avb_phy_int),
4178 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4179 SH_PFC_PIN_GROUP(avb_mdio),
4180 SH_PFC_PIN_GROUP(avb_mii),
4181 SH_PFC_PIN_GROUP(avb_avtp_pps),
4182 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4183 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4184 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4185 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4186 SH_PFC_PIN_GROUP(can0_data_a),
4187 SH_PFC_PIN_GROUP(can0_data_b),
4188 SH_PFC_PIN_GROUP(can1_data),
4189 SH_PFC_PIN_GROUP(can_clk),
4190 SH_PFC_PIN_GROUP(canfd0_data_a),
4191 SH_PFC_PIN_GROUP(canfd0_data_b),
4192 SH_PFC_PIN_GROUP(canfd1_data),
4193 SH_PFC_PIN_GROUP(du_rgb666),
4194 SH_PFC_PIN_GROUP(du_rgb888),
4195 SH_PFC_PIN_GROUP(du_clk_out_0),
4196 SH_PFC_PIN_GROUP(du_clk_out_1),
4197 SH_PFC_PIN_GROUP(du_sync),
4198 SH_PFC_PIN_GROUP(du_oddf),
4199 SH_PFC_PIN_GROUP(du_cde),
4200 SH_PFC_PIN_GROUP(du_disp),
4201 SH_PFC_PIN_GROUP(hscif0_data),
4202 SH_PFC_PIN_GROUP(hscif0_clk),
4203 SH_PFC_PIN_GROUP(hscif0_ctrl),
4204 SH_PFC_PIN_GROUP(hscif1_data_a),
4205 SH_PFC_PIN_GROUP(hscif1_clk_a),
4206 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4207 SH_PFC_PIN_GROUP(hscif1_data_b),
4208 SH_PFC_PIN_GROUP(hscif1_clk_b),
4209 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4210 SH_PFC_PIN_GROUP(hscif2_data_a),
4211 SH_PFC_PIN_GROUP(hscif2_clk_a),
4212 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4213 SH_PFC_PIN_GROUP(hscif2_data_b),
4214 SH_PFC_PIN_GROUP(hscif2_clk_b),
4215 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4216 SH_PFC_PIN_GROUP(hscif2_data_c),
4217 SH_PFC_PIN_GROUP(hscif2_clk_c),
4218 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4219 SH_PFC_PIN_GROUP(hscif3_data_a),
4220 SH_PFC_PIN_GROUP(hscif3_clk),
4221 SH_PFC_PIN_GROUP(hscif3_ctrl),
4222 SH_PFC_PIN_GROUP(hscif3_data_b),
4223 SH_PFC_PIN_GROUP(hscif3_data_c),
4224 SH_PFC_PIN_GROUP(hscif3_data_d),
4225 SH_PFC_PIN_GROUP(hscif4_data_a),
4226 SH_PFC_PIN_GROUP(hscif4_clk),
4227 SH_PFC_PIN_GROUP(hscif4_ctrl),
4228 SH_PFC_PIN_GROUP(hscif4_data_b),
4229 SH_PFC_PIN_GROUP(i2c0),
4230 SH_PFC_PIN_GROUP(i2c1_a),
4231 SH_PFC_PIN_GROUP(i2c1_b),
4232 SH_PFC_PIN_GROUP(i2c2_a),
4233 SH_PFC_PIN_GROUP(i2c2_b),
4234 SH_PFC_PIN_GROUP(i2c3),
4235 SH_PFC_PIN_GROUP(i2c5),
4236 SH_PFC_PIN_GROUP(i2c6_a),
4237 SH_PFC_PIN_GROUP(i2c6_b),
4238 SH_PFC_PIN_GROUP(i2c6_c),
4239 SH_PFC_PIN_GROUP(intc_ex_irq0),
4240 SH_PFC_PIN_GROUP(intc_ex_irq1),
4241 SH_PFC_PIN_GROUP(intc_ex_irq2),
4242 SH_PFC_PIN_GROUP(intc_ex_irq3),
4243 SH_PFC_PIN_GROUP(intc_ex_irq4),
4244 SH_PFC_PIN_GROUP(intc_ex_irq5),
4245 SH_PFC_PIN_GROUP(msiof0_clk),
4246 SH_PFC_PIN_GROUP(msiof0_sync),
4247 SH_PFC_PIN_GROUP(msiof0_ss1),
4248 SH_PFC_PIN_GROUP(msiof0_ss2),
4249 SH_PFC_PIN_GROUP(msiof0_txd),
4250 SH_PFC_PIN_GROUP(msiof0_rxd),
4251 SH_PFC_PIN_GROUP(msiof1_clk_a),
4252 SH_PFC_PIN_GROUP(msiof1_sync_a),
4253 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4254 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4255 SH_PFC_PIN_GROUP(msiof1_txd_a),
4256 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4257 SH_PFC_PIN_GROUP(msiof1_clk_b),
4258 SH_PFC_PIN_GROUP(msiof1_sync_b),
4259 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4260 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4261 SH_PFC_PIN_GROUP(msiof1_txd_b),
4262 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4263 SH_PFC_PIN_GROUP(msiof1_clk_c),
4264 SH_PFC_PIN_GROUP(msiof1_sync_c),
4265 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4266 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4267 SH_PFC_PIN_GROUP(msiof1_txd_c),
4268 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4269 SH_PFC_PIN_GROUP(msiof1_clk_d),
4270 SH_PFC_PIN_GROUP(msiof1_sync_d),
4271 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4272 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4273 SH_PFC_PIN_GROUP(msiof1_txd_d),
4274 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4275 SH_PFC_PIN_GROUP(msiof1_clk_e),
4276 SH_PFC_PIN_GROUP(msiof1_sync_e),
4277 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4278 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4279 SH_PFC_PIN_GROUP(msiof1_txd_e),
4280 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4281 SH_PFC_PIN_GROUP(msiof1_clk_f),
4282 SH_PFC_PIN_GROUP(msiof1_sync_f),
4283 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4284 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4285 SH_PFC_PIN_GROUP(msiof1_txd_f),
4286 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4287 SH_PFC_PIN_GROUP(msiof1_clk_g),
4288 SH_PFC_PIN_GROUP(msiof1_sync_g),
4289 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4290 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4291 SH_PFC_PIN_GROUP(msiof1_txd_g),
4292 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4293 SH_PFC_PIN_GROUP(msiof2_clk_a),
4294 SH_PFC_PIN_GROUP(msiof2_sync_a),
4295 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4296 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4297 SH_PFC_PIN_GROUP(msiof2_txd_a),
4298 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4299 SH_PFC_PIN_GROUP(msiof2_clk_b),
4300 SH_PFC_PIN_GROUP(msiof2_sync_b),
4301 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4302 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4303 SH_PFC_PIN_GROUP(msiof2_txd_b),
4304 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4305 SH_PFC_PIN_GROUP(msiof2_clk_c),
4306 SH_PFC_PIN_GROUP(msiof2_sync_c),
4307 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4308 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4309 SH_PFC_PIN_GROUP(msiof2_txd_c),
4310 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4311 SH_PFC_PIN_GROUP(msiof2_clk_d),
4312 SH_PFC_PIN_GROUP(msiof2_sync_d),
4313 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4314 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4315 SH_PFC_PIN_GROUP(msiof2_txd_d),
4316 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4317 SH_PFC_PIN_GROUP(msiof3_clk_a),
4318 SH_PFC_PIN_GROUP(msiof3_sync_a),
4319 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4320 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4321 SH_PFC_PIN_GROUP(msiof3_txd_a),
4322 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4323 SH_PFC_PIN_GROUP(msiof3_clk_b),
4324 SH_PFC_PIN_GROUP(msiof3_sync_b),
4325 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4326 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4327 SH_PFC_PIN_GROUP(msiof3_txd_b),
4328 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4329 SH_PFC_PIN_GROUP(msiof3_clk_c),
4330 SH_PFC_PIN_GROUP(msiof3_sync_c),
4331 SH_PFC_PIN_GROUP(msiof3_txd_c),
4332 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4333 SH_PFC_PIN_GROUP(msiof3_clk_d),
4334 SH_PFC_PIN_GROUP(msiof3_sync_d),
4335 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4336 SH_PFC_PIN_GROUP(msiof3_txd_d),
4337 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4338 SH_PFC_PIN_GROUP(msiof3_clk_e),
4339 SH_PFC_PIN_GROUP(msiof3_sync_e),
4340 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4341 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4342 SH_PFC_PIN_GROUP(msiof3_txd_e),
4343 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4344 SH_PFC_PIN_GROUP(pwm0),
4345 SH_PFC_PIN_GROUP(pwm1_a),
4346 SH_PFC_PIN_GROUP(pwm1_b),
4347 SH_PFC_PIN_GROUP(pwm2_a),
4348 SH_PFC_PIN_GROUP(pwm2_b),
4349 SH_PFC_PIN_GROUP(pwm3_a),
4350 SH_PFC_PIN_GROUP(pwm3_b),
4351 SH_PFC_PIN_GROUP(pwm4_a),
4352 SH_PFC_PIN_GROUP(pwm4_b),
4353 SH_PFC_PIN_GROUP(pwm5_a),
4354 SH_PFC_PIN_GROUP(pwm5_b),
4355 SH_PFC_PIN_GROUP(pwm6_a),
4356 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4357 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4358 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4359 BUS_DATA_PIN_GROUP(qspi0_data, 4),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4360 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4361 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4362 BUS_DATA_PIN_GROUP(qspi1_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4363 SH_PFC_PIN_GROUP(sata0_devslp_a),
4364 SH_PFC_PIN_GROUP(sata0_devslp_b),
4365 SH_PFC_PIN_GROUP(scif0_data),
4366 SH_PFC_PIN_GROUP(scif0_clk),
4367 SH_PFC_PIN_GROUP(scif0_ctrl),
4368 SH_PFC_PIN_GROUP(scif1_data_a),
4369 SH_PFC_PIN_GROUP(scif1_clk),
4370 SH_PFC_PIN_GROUP(scif1_ctrl),
4371 SH_PFC_PIN_GROUP(scif1_data_b),
4372 SH_PFC_PIN_GROUP(scif2_data_a),
4373 SH_PFC_PIN_GROUP(scif2_clk),
4374 SH_PFC_PIN_GROUP(scif2_data_b),
4375 SH_PFC_PIN_GROUP(scif3_data_a),
4376 SH_PFC_PIN_GROUP(scif3_clk),
4377 SH_PFC_PIN_GROUP(scif3_ctrl),
4378 SH_PFC_PIN_GROUP(scif3_data_b),
4379 SH_PFC_PIN_GROUP(scif4_data_a),
4380 SH_PFC_PIN_GROUP(scif4_clk_a),
4381 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4382 SH_PFC_PIN_GROUP(scif4_data_b),
4383 SH_PFC_PIN_GROUP(scif4_clk_b),
4384 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4385 SH_PFC_PIN_GROUP(scif4_data_c),
4386 SH_PFC_PIN_GROUP(scif4_clk_c),
4387 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4388 SH_PFC_PIN_GROUP(scif5_data_a),
4389 SH_PFC_PIN_GROUP(scif5_clk_a),
4390 SH_PFC_PIN_GROUP(scif5_data_b),
4391 SH_PFC_PIN_GROUP(scif5_clk_b),
4392 SH_PFC_PIN_GROUP(scif_clk_a),
4393 SH_PFC_PIN_GROUP(scif_clk_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4394 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4395 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4396 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4397 SH_PFC_PIN_GROUP(sdhi0_cd),
4398 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4399 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4400 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4401 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4402 SH_PFC_PIN_GROUP(sdhi1_cd),
4403 SH_PFC_PIN_GROUP(sdhi1_wp),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4404 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4405 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4406 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4407 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4408 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4409 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4410 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4411 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4412 SH_PFC_PIN_GROUP(sdhi2_ds),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4413 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4414 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4415 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4416 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4417 SH_PFC_PIN_GROUP(sdhi3_cd),
4418 SH_PFC_PIN_GROUP(sdhi3_wp),
4419 SH_PFC_PIN_GROUP(sdhi3_ds),
4420 SH_PFC_PIN_GROUP(ssi0_data),
4421 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4422 SH_PFC_PIN_GROUP(ssi1_data_a),
4423 SH_PFC_PIN_GROUP(ssi1_data_b),
4424 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4425 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4426 SH_PFC_PIN_GROUP(ssi2_data_a),
4427 SH_PFC_PIN_GROUP(ssi2_data_b),
4428 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4429 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4430 SH_PFC_PIN_GROUP(ssi3_data),
4431 SH_PFC_PIN_GROUP(ssi349_ctrl),
4432 SH_PFC_PIN_GROUP(ssi4_data),
4433 SH_PFC_PIN_GROUP(ssi4_ctrl),
4434 SH_PFC_PIN_GROUP(ssi5_data),
4435 SH_PFC_PIN_GROUP(ssi5_ctrl),
4436 SH_PFC_PIN_GROUP(ssi6_data),
4437 SH_PFC_PIN_GROUP(ssi6_ctrl),
4438 SH_PFC_PIN_GROUP(ssi7_data),
4439 SH_PFC_PIN_GROUP(ssi78_ctrl),
4440 SH_PFC_PIN_GROUP(ssi8_data),
4441 SH_PFC_PIN_GROUP(ssi9_data_a),
4442 SH_PFC_PIN_GROUP(ssi9_data_b),
4443 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4444 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4445 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4446 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4447 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4448 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4449 SH_PFC_PIN_GROUP(tpu_to0),
4450 SH_PFC_PIN_GROUP(tpu_to1),
4451 SH_PFC_PIN_GROUP(tpu_to2),
4452 SH_PFC_PIN_GROUP(tpu_to3),
4453 SH_PFC_PIN_GROUP(usb0),
4454 SH_PFC_PIN_GROUP(usb1),
4455 SH_PFC_PIN_GROUP(usb2),
4456 SH_PFC_PIN_GROUP(usb2_ch3),
4457 SH_PFC_PIN_GROUP(usb30),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4458 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4459 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4460 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4461 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4462 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4463 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4464 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4465 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4466 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4467 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4468 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4469 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4470 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4471 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4472 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4473 SH_PFC_PIN_GROUP(vin4_sync),
4474 SH_PFC_PIN_GROUP(vin4_field),
4475 SH_PFC_PIN_GROUP(vin4_clkenb),
4476 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4477 BUS_DATA_PIN_GROUP(vin5_data, 8),
4478 BUS_DATA_PIN_GROUP(vin5_data, 10),
4479 BUS_DATA_PIN_GROUP(vin5_data, 12),
4480 BUS_DATA_PIN_GROUP(vin5_data, 16),
4481 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4482 SH_PFC_PIN_GROUP(vin5_sync),
4483 SH_PFC_PIN_GROUP(vin5_field),
4484 SH_PFC_PIN_GROUP(vin5_clkenb),
4485 SH_PFC_PIN_GROUP(vin5_clk),
4486 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4487#ifdef CONFIG_PINCTRL_PFC_R8A77951
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4488 .automotive = {
4489 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4490 SH_PFC_PIN_GROUP(drif0_data0_a),
4491 SH_PFC_PIN_GROUP(drif0_data1_a),
4492 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4493 SH_PFC_PIN_GROUP(drif0_data0_b),
4494 SH_PFC_PIN_GROUP(drif0_data1_b),
4495 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4496 SH_PFC_PIN_GROUP(drif0_data0_c),
4497 SH_PFC_PIN_GROUP(drif0_data1_c),
4498 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4499 SH_PFC_PIN_GROUP(drif1_data0_a),
4500 SH_PFC_PIN_GROUP(drif1_data1_a),
4501 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4502 SH_PFC_PIN_GROUP(drif1_data0_b),
4503 SH_PFC_PIN_GROUP(drif1_data1_b),
4504 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4505 SH_PFC_PIN_GROUP(drif1_data0_c),
4506 SH_PFC_PIN_GROUP(drif1_data1_c),
4507 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4508 SH_PFC_PIN_GROUP(drif2_data0_a),
4509 SH_PFC_PIN_GROUP(drif2_data1_a),
4510 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4511 SH_PFC_PIN_GROUP(drif2_data0_b),
4512 SH_PFC_PIN_GROUP(drif2_data1_b),
4513 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4514 SH_PFC_PIN_GROUP(drif3_data0_a),
4515 SH_PFC_PIN_GROUP(drif3_data1_a),
4516 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4517 SH_PFC_PIN_GROUP(drif3_data0_b),
4518 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4519 SH_PFC_PIN_GROUP(mlb_3pin),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4520 }
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4521#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4522};
4523
4524static const char * const audio_clk_groups[] = {
4525 "audio_clk_a_a",
4526 "audio_clk_a_b",
4527 "audio_clk_a_c",
4528 "audio_clk_b_a",
4529 "audio_clk_b_b",
4530 "audio_clk_c_a",
4531 "audio_clk_c_b",
4532 "audio_clkout_a",
4533 "audio_clkout_b",
4534 "audio_clkout_c",
4535 "audio_clkout_d",
4536 "audio_clkout1_a",
4537 "audio_clkout1_b",
4538 "audio_clkout2_a",
4539 "audio_clkout2_b",
4540 "audio_clkout3_a",
4541 "audio_clkout3_b",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4542};
4543
4544static const char * const avb_groups[] = {
4545 "avb_link",
4546 "avb_magic",
4547 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4548 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4549 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4550 "avb_mii",
4551 "avb_avtp_pps",
4552 "avb_avtp_match_a",
4553 "avb_avtp_capture_a",
4554 "avb_avtp_match_b",
4555 "avb_avtp_capture_b",
4556};
4557
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4558static const char * const can0_groups[] = {
4559 "can0_data_a",
4560 "can0_data_b",
4561};
4562
4563static const char * const can1_groups[] = {
4564 "can1_data",
4565};
4566
4567static const char * const can_clk_groups[] = {
4568 "can_clk",
4569};
4570
4571static const char * const canfd0_groups[] = {
4572 "canfd0_data_a",
4573 "canfd0_data_b",
4574};
4575
4576static const char * const canfd1_groups[] = {
4577 "canfd1_data",
4578};
4579
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4580#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4581static const char * const drif0_groups[] = {
4582 "drif0_ctrl_a",
4583 "drif0_data0_a",
4584 "drif0_data1_a",
4585 "drif0_ctrl_b",
4586 "drif0_data0_b",
4587 "drif0_data1_b",
4588 "drif0_ctrl_c",
4589 "drif0_data0_c",
4590 "drif0_data1_c",
4591};
4592
4593static const char * const drif1_groups[] = {
4594 "drif1_ctrl_a",
4595 "drif1_data0_a",
4596 "drif1_data1_a",
4597 "drif1_ctrl_b",
4598 "drif1_data0_b",
4599 "drif1_data1_b",
4600 "drif1_ctrl_c",
4601 "drif1_data0_c",
4602 "drif1_data1_c",
4603};
4604
4605static const char * const drif2_groups[] = {
4606 "drif2_ctrl_a",
4607 "drif2_data0_a",
4608 "drif2_data1_a",
4609 "drif2_ctrl_b",
4610 "drif2_data0_b",
4611 "drif2_data1_b",
4612};
4613
4614static const char * const drif3_groups[] = {
4615 "drif3_ctrl_a",
4616 "drif3_data0_a",
4617 "drif3_data1_a",
4618 "drif3_ctrl_b",
4619 "drif3_data0_b",
4620 "drif3_data1_b",
4621};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4622#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4623
4624static const char * const du_groups[] = {
4625 "du_rgb666",
4626 "du_rgb888",
4627 "du_clk_out_0",
4628 "du_clk_out_1",
4629 "du_sync",
4630 "du_oddf",
4631 "du_cde",
4632 "du_disp",
4633};
4634
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4635static const char * const hscif0_groups[] = {
4636 "hscif0_data",
4637 "hscif0_clk",
4638 "hscif0_ctrl",
4639};
4640
4641static const char * const hscif1_groups[] = {
4642 "hscif1_data_a",
4643 "hscif1_clk_a",
4644 "hscif1_ctrl_a",
4645 "hscif1_data_b",
4646 "hscif1_clk_b",
4647 "hscif1_ctrl_b",
4648};
4649
4650static const char * const hscif2_groups[] = {
4651 "hscif2_data_a",
4652 "hscif2_clk_a",
4653 "hscif2_ctrl_a",
4654 "hscif2_data_b",
4655 "hscif2_clk_b",
4656 "hscif2_ctrl_b",
4657 "hscif2_data_c",
4658 "hscif2_clk_c",
4659 "hscif2_ctrl_c",
4660};
4661
4662static const char * const hscif3_groups[] = {
4663 "hscif3_data_a",
4664 "hscif3_clk",
4665 "hscif3_ctrl",
4666 "hscif3_data_b",
4667 "hscif3_data_c",
4668 "hscif3_data_d",
4669};
4670
4671static const char * const hscif4_groups[] = {
4672 "hscif4_data_a",
4673 "hscif4_clk",
4674 "hscif4_ctrl",
4675 "hscif4_data_b",
4676};
4677
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4678static const char * const i2c0_groups[] = {
4679 "i2c0",
4680};
4681
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4682static const char * const i2c1_groups[] = {
4683 "i2c1_a",
4684 "i2c1_b",
4685};
4686
4687static const char * const i2c2_groups[] = {
4688 "i2c2_a",
4689 "i2c2_b",
4690};
4691
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4692static const char * const i2c3_groups[] = {
4693 "i2c3",
4694};
4695
4696static const char * const i2c5_groups[] = {
4697 "i2c5",
4698};
4699
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4700static const char * const i2c6_groups[] = {
4701 "i2c6_a",
4702 "i2c6_b",
4703 "i2c6_c",
4704};
4705
4706static const char * const intc_ex_groups[] = {
4707 "intc_ex_irq0",
4708 "intc_ex_irq1",
4709 "intc_ex_irq2",
4710 "intc_ex_irq3",
4711 "intc_ex_irq4",
4712 "intc_ex_irq5",
4713};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4714
4715#ifdef CONFIG_PINCTRL_PFC_R8A77951
4716static const char * const mlb_3pin_groups[] = {
4717 "mlb_3pin",
4718};
4719#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4720
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4721static const char * const msiof0_groups[] = {
4722 "msiof0_clk",
4723 "msiof0_sync",
4724 "msiof0_ss1",
4725 "msiof0_ss2",
4726 "msiof0_txd",
4727 "msiof0_rxd",
4728};
4729
4730static const char * const msiof1_groups[] = {
4731 "msiof1_clk_a",
4732 "msiof1_sync_a",
4733 "msiof1_ss1_a",
4734 "msiof1_ss2_a",
4735 "msiof1_txd_a",
4736 "msiof1_rxd_a",
4737 "msiof1_clk_b",
4738 "msiof1_sync_b",
4739 "msiof1_ss1_b",
4740 "msiof1_ss2_b",
4741 "msiof1_txd_b",
4742 "msiof1_rxd_b",
4743 "msiof1_clk_c",
4744 "msiof1_sync_c",
4745 "msiof1_ss1_c",
4746 "msiof1_ss2_c",
4747 "msiof1_txd_c",
4748 "msiof1_rxd_c",
4749 "msiof1_clk_d",
4750 "msiof1_sync_d",
4751 "msiof1_ss1_d",
4752 "msiof1_ss2_d",
4753 "msiof1_txd_d",
4754 "msiof1_rxd_d",
4755 "msiof1_clk_e",
4756 "msiof1_sync_e",
4757 "msiof1_ss1_e",
4758 "msiof1_ss2_e",
4759 "msiof1_txd_e",
4760 "msiof1_rxd_e",
4761 "msiof1_clk_f",
4762 "msiof1_sync_f",
4763 "msiof1_ss1_f",
4764 "msiof1_ss2_f",
4765 "msiof1_txd_f",
4766 "msiof1_rxd_f",
4767 "msiof1_clk_g",
4768 "msiof1_sync_g",
4769 "msiof1_ss1_g",
4770 "msiof1_ss2_g",
4771 "msiof1_txd_g",
4772 "msiof1_rxd_g",
4773};
4774
4775static const char * const msiof2_groups[] = {
4776 "msiof2_clk_a",
4777 "msiof2_sync_a",
4778 "msiof2_ss1_a",
4779 "msiof2_ss2_a",
4780 "msiof2_txd_a",
4781 "msiof2_rxd_a",
4782 "msiof2_clk_b",
4783 "msiof2_sync_b",
4784 "msiof2_ss1_b",
4785 "msiof2_ss2_b",
4786 "msiof2_txd_b",
4787 "msiof2_rxd_b",
4788 "msiof2_clk_c",
4789 "msiof2_sync_c",
4790 "msiof2_ss1_c",
4791 "msiof2_ss2_c",
4792 "msiof2_txd_c",
4793 "msiof2_rxd_c",
4794 "msiof2_clk_d",
4795 "msiof2_sync_d",
4796 "msiof2_ss1_d",
4797 "msiof2_ss2_d",
4798 "msiof2_txd_d",
4799 "msiof2_rxd_d",
4800};
4801
4802static const char * const msiof3_groups[] = {
4803 "msiof3_clk_a",
4804 "msiof3_sync_a",
4805 "msiof3_ss1_a",
4806 "msiof3_ss2_a",
4807 "msiof3_txd_a",
4808 "msiof3_rxd_a",
4809 "msiof3_clk_b",
4810 "msiof3_sync_b",
4811 "msiof3_ss1_b",
4812 "msiof3_ss2_b",
4813 "msiof3_txd_b",
4814 "msiof3_rxd_b",
4815 "msiof3_clk_c",
4816 "msiof3_sync_c",
4817 "msiof3_txd_c",
4818 "msiof3_rxd_c",
4819 "msiof3_clk_d",
4820 "msiof3_sync_d",
4821 "msiof3_ss1_d",
4822 "msiof3_txd_d",
4823 "msiof3_rxd_d",
4824 "msiof3_clk_e",
4825 "msiof3_sync_e",
4826 "msiof3_ss1_e",
4827 "msiof3_ss2_e",
4828 "msiof3_txd_e",
4829 "msiof3_rxd_e",
4830};
4831
4832static const char * const pwm0_groups[] = {
4833 "pwm0",
4834};
4835
4836static const char * const pwm1_groups[] = {
4837 "pwm1_a",
4838 "pwm1_b",
4839};
4840
4841static const char * const pwm2_groups[] = {
4842 "pwm2_a",
4843 "pwm2_b",
4844};
4845
4846static const char * const pwm3_groups[] = {
4847 "pwm3_a",
4848 "pwm3_b",
4849};
4850
4851static const char * const pwm4_groups[] = {
4852 "pwm4_a",
4853 "pwm4_b",
4854};
4855
4856static const char * const pwm5_groups[] = {
4857 "pwm5_a",
4858 "pwm5_b",
4859};
4860
4861static const char * const pwm6_groups[] = {
4862 "pwm6_a",
4863 "pwm6_b",
4864};
4865
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4866static const char * const qspi0_groups[] = {
4867 "qspi0_ctrl",
4868 "qspi0_data2",
4869 "qspi0_data4",
4870};
4871
4872static const char * const qspi1_groups[] = {
4873 "qspi1_ctrl",
4874 "qspi1_data2",
4875 "qspi1_data4",
4876};
4877
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4878static const char * const sata0_groups[] = {
4879 "sata0_devslp_a",
4880 "sata0_devslp_b",
4881};
4882
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4883static const char * const scif0_groups[] = {
4884 "scif0_data",
4885 "scif0_clk",
4886 "scif0_ctrl",
4887};
4888
4889static const char * const scif1_groups[] = {
4890 "scif1_data_a",
4891 "scif1_clk",
4892 "scif1_ctrl",
4893 "scif1_data_b",
4894};
4895
4896static const char * const scif2_groups[] = {
4897 "scif2_data_a",
4898 "scif2_clk",
4899 "scif2_data_b",
4900};
4901
4902static const char * const scif3_groups[] = {
4903 "scif3_data_a",
4904 "scif3_clk",
4905 "scif3_ctrl",
4906 "scif3_data_b",
4907};
4908
4909static const char * const scif4_groups[] = {
4910 "scif4_data_a",
4911 "scif4_clk_a",
4912 "scif4_ctrl_a",
4913 "scif4_data_b",
4914 "scif4_clk_b",
4915 "scif4_ctrl_b",
4916 "scif4_data_c",
4917 "scif4_clk_c",
4918 "scif4_ctrl_c",
4919};
4920
4921static const char * const scif5_groups[] = {
4922 "scif5_data_a",
4923 "scif5_clk_a",
4924 "scif5_data_b",
4925 "scif5_clk_b",
4926};
4927
4928static const char * const scif_clk_groups[] = {
4929 "scif_clk_a",
4930 "scif_clk_b",
4931};
4932
4933static const char * const sdhi0_groups[] = {
4934 "sdhi0_data1",
4935 "sdhi0_data4",
4936 "sdhi0_ctrl",
4937 "sdhi0_cd",
4938 "sdhi0_wp",
4939};
4940
4941static const char * const sdhi1_groups[] = {
4942 "sdhi1_data1",
4943 "sdhi1_data4",
4944 "sdhi1_ctrl",
4945 "sdhi1_cd",
4946 "sdhi1_wp",
4947};
4948
4949static const char * const sdhi2_groups[] = {
4950 "sdhi2_data1",
4951 "sdhi2_data4",
4952 "sdhi2_data8",
4953 "sdhi2_ctrl",
4954 "sdhi2_cd_a",
4955 "sdhi2_wp_a",
4956 "sdhi2_cd_b",
4957 "sdhi2_wp_b",
4958 "sdhi2_ds",
4959};
4960
4961static const char * const sdhi3_groups[] = {
4962 "sdhi3_data1",
4963 "sdhi3_data4",
4964 "sdhi3_data8",
4965 "sdhi3_ctrl",
4966 "sdhi3_cd",
4967 "sdhi3_wp",
4968 "sdhi3_ds",
4969};
4970
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4971static const char * const ssi_groups[] = {
4972 "ssi0_data",
4973 "ssi01239_ctrl",
4974 "ssi1_data_a",
4975 "ssi1_data_b",
4976 "ssi1_ctrl_a",
4977 "ssi1_ctrl_b",
4978 "ssi2_data_a",
4979 "ssi2_data_b",
4980 "ssi2_ctrl_a",
4981 "ssi2_ctrl_b",
4982 "ssi3_data",
4983 "ssi349_ctrl",
4984 "ssi4_data",
4985 "ssi4_ctrl",
4986 "ssi5_data",
4987 "ssi5_ctrl",
4988 "ssi6_data",
4989 "ssi6_ctrl",
4990 "ssi7_data",
4991 "ssi78_ctrl",
4992 "ssi8_data",
4993 "ssi9_data_a",
4994 "ssi9_data_b",
4995 "ssi9_ctrl_a",
4996 "ssi9_ctrl_b",
4997};
4998
4999static const char * const tmu_groups[] = {
5000 "tmu_tclk1_a",
5001 "tmu_tclk1_b",
5002 "tmu_tclk2_a",
5003 "tmu_tclk2_b",
5004};
5005
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5006static const char * const tpu_groups[] = {
5007 "tpu_to0",
5008 "tpu_to1",
5009 "tpu_to2",
5010 "tpu_to3",
5011};
5012
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5013static const char * const usb0_groups[] = {
5014 "usb0",
5015};
5016
5017static const char * const usb1_groups[] = {
5018 "usb1",
5019};
5020
5021static const char * const usb2_groups[] = {
5022 "usb2",
5023};
5024
5025static const char * const usb2_ch3_groups[] = {
5026 "usb2_ch3",
5027};
5028
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5029static const char * const usb30_groups[] = {
5030 "usb30",
5031};
5032
5033static const char * const vin4_groups[] = {
5034 "vin4_data8_a",
5035 "vin4_data10_a",
5036 "vin4_data12_a",
5037 "vin4_data16_a",
5038 "vin4_data18_a",
5039 "vin4_data20_a",
5040 "vin4_data24_a",
5041 "vin4_data8_b",
5042 "vin4_data10_b",
5043 "vin4_data12_b",
5044 "vin4_data16_b",
5045 "vin4_data18_b",
5046 "vin4_data20_b",
5047 "vin4_data24_b",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5048 "vin4_g8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5049 "vin4_sync",
5050 "vin4_field",
5051 "vin4_clkenb",
5052 "vin4_clk",
5053};
5054
5055static const char * const vin5_groups[] = {
5056 "vin5_data8",
5057 "vin5_data10",
5058 "vin5_data12",
5059 "vin5_data16",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5060 "vin5_high8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5061 "vin5_sync",
5062 "vin5_field",
5063 "vin5_clkenb",
5064 "vin5_clk",
5065};
5066
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5067static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5068 struct sh_pfc_function common[55];
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5069#ifdef CONFIG_PINCTRL_PFC_R8A77951
5070 struct sh_pfc_function automotive[5];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]5071#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5072} pinmux_functions = {
5073 .common = {
5074 SH_PFC_FUNCTION(audio_clk),
5075 SH_PFC_FUNCTION(avb),
5076 SH_PFC_FUNCTION(can0),
5077 SH_PFC_FUNCTION(can1),
5078 SH_PFC_FUNCTION(can_clk),
5079 SH_PFC_FUNCTION(canfd0),
5080 SH_PFC_FUNCTION(canfd1),
5081 SH_PFC_FUNCTION(du),
5082 SH_PFC_FUNCTION(hscif0),
5083 SH_PFC_FUNCTION(hscif1),
5084 SH_PFC_FUNCTION(hscif2),
5085 SH_PFC_FUNCTION(hscif3),
5086 SH_PFC_FUNCTION(hscif4),
5087 SH_PFC_FUNCTION(i2c0),
5088 SH_PFC_FUNCTION(i2c1),
5089 SH_PFC_FUNCTION(i2c2),
5090 SH_PFC_FUNCTION(i2c3),
5091 SH_PFC_FUNCTION(i2c5),
5092 SH_PFC_FUNCTION(i2c6),
5093 SH_PFC_FUNCTION(intc_ex),
5094 SH_PFC_FUNCTION(msiof0),
5095 SH_PFC_FUNCTION(msiof1),
5096 SH_PFC_FUNCTION(msiof2),
5097 SH_PFC_FUNCTION(msiof3),
5098 SH_PFC_FUNCTION(pwm0),
5099 SH_PFC_FUNCTION(pwm1),
5100 SH_PFC_FUNCTION(pwm2),
5101 SH_PFC_FUNCTION(pwm3),
5102 SH_PFC_FUNCTION(pwm4),
5103 SH_PFC_FUNCTION(pwm5),
5104 SH_PFC_FUNCTION(pwm6),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5105 SH_PFC_FUNCTION(qspi0),
5106 SH_PFC_FUNCTION(qspi1),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5107 SH_PFC_FUNCTION(sata0),
5108 SH_PFC_FUNCTION(scif0),
5109 SH_PFC_FUNCTION(scif1),
5110 SH_PFC_FUNCTION(scif2),
5111 SH_PFC_FUNCTION(scif3),
5112 SH_PFC_FUNCTION(scif4),
5113 SH_PFC_FUNCTION(scif5),
5114 SH_PFC_FUNCTION(scif_clk),
5115 SH_PFC_FUNCTION(sdhi0),
5116 SH_PFC_FUNCTION(sdhi1),
5117 SH_PFC_FUNCTION(sdhi2),
5118 SH_PFC_FUNCTION(sdhi3),
5119 SH_PFC_FUNCTION(ssi),
5120 SH_PFC_FUNCTION(tmu),
5121 SH_PFC_FUNCTION(tpu),
5122 SH_PFC_FUNCTION(usb0),
5123 SH_PFC_FUNCTION(usb1),
5124 SH_PFC_FUNCTION(usb2),
5125 SH_PFC_FUNCTION(usb2_ch3),
5126 SH_PFC_FUNCTION(usb30),
5127 SH_PFC_FUNCTION(vin4),
5128 SH_PFC_FUNCTION(vin5),
5129 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5130#ifdef CONFIG_PINCTRL_PFC_R8A77951
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5131 .automotive = {
5132 SH_PFC_FUNCTION(drif0),
5133 SH_PFC_FUNCTION(drif1),
5134 SH_PFC_FUNCTION(drif2),
5135 SH_PFC_FUNCTION(drif3),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5136 SH_PFC_FUNCTION(mlb_3pin),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5137 }
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5138#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5139};
5140
5141static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5142#define F_(x, y) FN_##y
5143#define FM(x) FN_##x
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5144 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5145 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5146 1, 1, 1, 1, 1),
5147 GROUP(
5148 /* GP0_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5149 GP_0_15_FN, GPSR0_15,
5150 GP_0_14_FN, GPSR0_14,
5151 GP_0_13_FN, GPSR0_13,
5152 GP_0_12_FN, GPSR0_12,
5153 GP_0_11_FN, GPSR0_11,
5154 GP_0_10_FN, GPSR0_10,
5155 GP_0_9_FN, GPSR0_9,
5156 GP_0_8_FN, GPSR0_8,
5157 GP_0_7_FN, GPSR0_7,
5158 GP_0_6_FN, GPSR0_6,
5159 GP_0_5_FN, GPSR0_5,
5160 GP_0_4_FN, GPSR0_4,
5161 GP_0_3_FN, GPSR0_3,
5162 GP_0_2_FN, GPSR0_2,
5163 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5164 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5165 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5166 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5167 0, 0,
5168 0, 0,
5169 0, 0,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5170 GP_1_28_FN, GPSR1_28,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5171 GP_1_27_FN, GPSR1_27,
5172 GP_1_26_FN, GPSR1_26,
5173 GP_1_25_FN, GPSR1_25,
5174 GP_1_24_FN, GPSR1_24,
5175 GP_1_23_FN, GPSR1_23,
5176 GP_1_22_FN, GPSR1_22,
5177 GP_1_21_FN, GPSR1_21,
5178 GP_1_20_FN, GPSR1_20,
5179 GP_1_19_FN, GPSR1_19,
5180 GP_1_18_FN, GPSR1_18,
5181 GP_1_17_FN, GPSR1_17,
5182 GP_1_16_FN, GPSR1_16,
5183 GP_1_15_FN, GPSR1_15,
5184 GP_1_14_FN, GPSR1_14,
5185 GP_1_13_FN, GPSR1_13,
5186 GP_1_12_FN, GPSR1_12,
5187 GP_1_11_FN, GPSR1_11,
5188 GP_1_10_FN, GPSR1_10,
5189 GP_1_9_FN, GPSR1_9,
5190 GP_1_8_FN, GPSR1_8,
5191 GP_1_7_FN, GPSR1_7,
5192 GP_1_6_FN, GPSR1_6,
5193 GP_1_5_FN, GPSR1_5,
5194 GP_1_4_FN, GPSR1_4,
5195 GP_1_3_FN, GPSR1_3,
5196 GP_1_2_FN, GPSR1_2,
5197 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5198 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5199 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5200 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5201 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5202 1, 1, 1, 1),
5203 GROUP(
5204 /* GP2_31_15 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5205 GP_2_14_FN, GPSR2_14,
5206 GP_2_13_FN, GPSR2_13,
5207 GP_2_12_FN, GPSR2_12,
5208 GP_2_11_FN, GPSR2_11,
5209 GP_2_10_FN, GPSR2_10,
5210 GP_2_9_FN, GPSR2_9,
5211 GP_2_8_FN, GPSR2_8,
5212 GP_2_7_FN, GPSR2_7,
5213 GP_2_6_FN, GPSR2_6,
5214 GP_2_5_FN, GPSR2_5,
5215 GP_2_4_FN, GPSR2_4,
5216 GP_2_3_FN, GPSR2_3,
5217 GP_2_2_FN, GPSR2_2,
5218 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5219 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5220 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5221 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5222 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5223 1, 1, 1, 1, 1),
5224 GROUP(
5225 /* GP3_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5226 GP_3_15_FN, GPSR3_15,
5227 GP_3_14_FN, GPSR3_14,
5228 GP_3_13_FN, GPSR3_13,
5229 GP_3_12_FN, GPSR3_12,
5230 GP_3_11_FN, GPSR3_11,
5231 GP_3_10_FN, GPSR3_10,
5232 GP_3_9_FN, GPSR3_9,
5233 GP_3_8_FN, GPSR3_8,
5234 GP_3_7_FN, GPSR3_7,
5235 GP_3_6_FN, GPSR3_6,
5236 GP_3_5_FN, GPSR3_5,
5237 GP_3_4_FN, GPSR3_4,
5238 GP_3_3_FN, GPSR3_3,
5239 GP_3_2_FN, GPSR3_2,
5240 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5241 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5242 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5243 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5244 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5245 1, 1, 1, 1, 1, 1, 1),
5246 GROUP(
5247 /* GP4_31_18 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5248 GP_4_17_FN, GPSR4_17,
5249 GP_4_16_FN, GPSR4_16,
5250 GP_4_15_FN, GPSR4_15,
5251 GP_4_14_FN, GPSR4_14,
5252 GP_4_13_FN, GPSR4_13,
5253 GP_4_12_FN, GPSR4_12,
5254 GP_4_11_FN, GPSR4_11,
5255 GP_4_10_FN, GPSR4_10,
5256 GP_4_9_FN, GPSR4_9,
5257 GP_4_8_FN, GPSR4_8,
5258 GP_4_7_FN, GPSR4_7,
5259 GP_4_6_FN, GPSR4_6,
5260 GP_4_5_FN, GPSR4_5,
5261 GP_4_4_FN, GPSR4_4,
5262 GP_4_3_FN, GPSR4_3,
5263 GP_4_2_FN, GPSR4_2,
5264 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5265 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5266 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5267 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5268 0, 0,
5269 0, 0,
5270 0, 0,
5271 0, 0,
5272 0, 0,
5273 0, 0,
5274 GP_5_25_FN, GPSR5_25,
5275 GP_5_24_FN, GPSR5_24,
5276 GP_5_23_FN, GPSR5_23,
5277 GP_5_22_FN, GPSR5_22,
5278 GP_5_21_FN, GPSR5_21,
5279 GP_5_20_FN, GPSR5_20,
5280 GP_5_19_FN, GPSR5_19,
5281 GP_5_18_FN, GPSR5_18,
5282 GP_5_17_FN, GPSR5_17,
5283 GP_5_16_FN, GPSR5_16,
5284 GP_5_15_FN, GPSR5_15,
5285 GP_5_14_FN, GPSR5_14,
5286 GP_5_13_FN, GPSR5_13,
5287 GP_5_12_FN, GPSR5_12,
5288 GP_5_11_FN, GPSR5_11,
5289 GP_5_10_FN, GPSR5_10,
5290 GP_5_9_FN, GPSR5_9,
5291 GP_5_8_FN, GPSR5_8,
5292 GP_5_7_FN, GPSR5_7,
5293 GP_5_6_FN, GPSR5_6,
5294 GP_5_5_FN, GPSR5_5,
5295 GP_5_4_FN, GPSR5_4,
5296 GP_5_3_FN, GPSR5_3,
5297 GP_5_2_FN, GPSR5_2,
5298 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5299 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5300 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5301 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5302 GP_6_31_FN, GPSR6_31,
5303 GP_6_30_FN, GPSR6_30,
5304 GP_6_29_FN, GPSR6_29,
5305 GP_6_28_FN, GPSR6_28,
5306 GP_6_27_FN, GPSR6_27,
5307 GP_6_26_FN, GPSR6_26,
5308 GP_6_25_FN, GPSR6_25,
5309 GP_6_24_FN, GPSR6_24,
5310 GP_6_23_FN, GPSR6_23,
5311 GP_6_22_FN, GPSR6_22,
5312 GP_6_21_FN, GPSR6_21,
5313 GP_6_20_FN, GPSR6_20,
5314 GP_6_19_FN, GPSR6_19,
5315 GP_6_18_FN, GPSR6_18,
5316 GP_6_17_FN, GPSR6_17,
5317 GP_6_16_FN, GPSR6_16,
5318 GP_6_15_FN, GPSR6_15,
5319 GP_6_14_FN, GPSR6_14,
5320 GP_6_13_FN, GPSR6_13,
5321 GP_6_12_FN, GPSR6_12,
5322 GP_6_11_FN, GPSR6_11,
5323 GP_6_10_FN, GPSR6_10,
5324 GP_6_9_FN, GPSR6_9,
5325 GP_6_8_FN, GPSR6_8,
5326 GP_6_7_FN, GPSR6_7,
5327 GP_6_6_FN, GPSR6_6,
5328 GP_6_5_FN, GPSR6_5,
5329 GP_6_4_FN, GPSR6_4,
5330 GP_6_3_FN, GPSR6_3,
5331 GP_6_2_FN, GPSR6_2,
5332 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5333 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5334 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5335 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5336 GROUP(-28, 1, 1, 1, 1),
5337 GROUP(
5338 /* GP7_31_4 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5339 GP_7_3_FN, GPSR7_3,
5340 GP_7_2_FN, GPSR7_2,
5341 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5342 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5343 },
5344#undef F_
5345#undef FM
5346
5347#define F_(x, y) x,
5348#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5349 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5350 IP0_31_28
5351 IP0_27_24
5352 IP0_23_20
5353 IP0_19_16
5354 IP0_15_12
5355 IP0_11_8
5356 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5357 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5358 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5359 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5360 IP1_31_28
5361 IP1_27_24
5362 IP1_23_20
5363 IP1_19_16
5364 IP1_15_12
5365 IP1_11_8
5366 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5367 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5368 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5369 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5370 IP2_31_28
5371 IP2_27_24
5372 IP2_23_20
5373 IP2_19_16
5374 IP2_15_12
5375 IP2_11_8
5376 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5377 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5378 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5379 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5380 IP3_31_28
5381 IP3_27_24
5382 IP3_23_20
5383 IP3_19_16
5384 IP3_15_12
5385 IP3_11_8
5386 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5387 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5388 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5389 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5390 IP4_31_28
5391 IP4_27_24
5392 IP4_23_20
5393 IP4_19_16
5394 IP4_15_12
5395 IP4_11_8
5396 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5397 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5398 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5399 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5400 IP5_31_28
5401 IP5_27_24
5402 IP5_23_20
5403 IP5_19_16
5404 IP5_15_12
5405 IP5_11_8
5406 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5407 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5408 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5409 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5410 IP6_31_28
5411 IP6_27_24
5412 IP6_23_20
5413 IP6_19_16
5414 IP6_15_12
5415 IP6_11_8
5416 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5417 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5418 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5419 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5420 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5421 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5422 IP7_31_28
5423 IP7_27_24
5424 IP7_23_20
5425 IP7_19_16
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5426 /* IP7_15_12 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5427 IP7_11_8
5428 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5429 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5430 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5431 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5432 IP8_31_28
5433 IP8_27_24
5434 IP8_23_20
5435 IP8_19_16
5436 IP8_15_12
5437 IP8_11_8
5438 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5439 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5440 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5441 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5442 IP9_31_28
5443 IP9_27_24
5444 IP9_23_20
5445 IP9_19_16
5446 IP9_15_12
5447 IP9_11_8
5448 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5449 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5450 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5451 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5452 IP10_31_28
5453 IP10_27_24
5454 IP10_23_20
5455 IP10_19_16
5456 IP10_15_12
5457 IP10_11_8
5458 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5459 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5460 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5461 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5462 IP11_31_28
5463 IP11_27_24
5464 IP11_23_20
5465 IP11_19_16
5466 IP11_15_12
5467 IP11_11_8
5468 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5469 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5470 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5471 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5472 IP12_31_28
5473 IP12_27_24
5474 IP12_23_20
5475 IP12_19_16
5476 IP12_15_12
5477 IP12_11_8
5478 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5479 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5480 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5481 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5482 IP13_31_28
5483 IP13_27_24
5484 IP13_23_20
5485 IP13_19_16
5486 IP13_15_12
5487 IP13_11_8
5488 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5489 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5490 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5491 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5492 IP14_31_28
5493 IP14_27_24
5494 IP14_23_20
5495 IP14_19_16
5496 IP14_15_12
5497 IP14_11_8
5498 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5499 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5500 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5501 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5502 IP15_31_28
5503 IP15_27_24
5504 IP15_23_20
5505 IP15_19_16
5506 IP15_15_12
5507 IP15_11_8
5508 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5509 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5510 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5511 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5512 IP16_31_28
5513 IP16_27_24
5514 IP16_23_20
5515 IP16_19_16
5516 IP16_15_12
5517 IP16_11_8
5518 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5519 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5520 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5521 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5522 IP17_31_28
5523 IP17_27_24
5524 IP17_23_20
5525 IP17_19_16
5526 IP17_15_12
5527 IP17_11_8
5528 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5529 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5530 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5531 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5532 GROUP(-24, 4, 4),
5533 GROUP(
5534 /* IP18_31_8 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5535 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5536 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5537 },
5538#undef F_
5539#undef FM
5540
5541#define F_(x, y) x,
5542#define FM(x) FN_##x,
5543 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5544 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5545 1, 1, 1, 2, 2, 1, 2, -3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5546 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5547 MOD_SEL0_31_30_29
5548 MOD_SEL0_28_27
5549 MOD_SEL0_26_25_24
5550 MOD_SEL0_23
5551 MOD_SEL0_22
5552 MOD_SEL0_21
5553 MOD_SEL0_20
5554 MOD_SEL0_19
5555 MOD_SEL0_18_17
5556 MOD_SEL0_16
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5557 /* RESERVED 15 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5558 MOD_SEL0_14_13
5559 MOD_SEL0_12
5560 MOD_SEL0_11
5561 MOD_SEL0_10
5562 MOD_SEL0_9_8
5563 MOD_SEL0_7_6
5564 MOD_SEL0_5
5565 MOD_SEL0_4_3
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5566 /* RESERVED 2, 1, 0 */ ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5567 },
5568 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5569 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5570 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5571 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5572 MOD_SEL1_31_30
5573 MOD_SEL1_29_28_27
5574 MOD_SEL1_26
5575 MOD_SEL1_25_24
5576 MOD_SEL1_23_22_21
5577 MOD_SEL1_20
5578 MOD_SEL1_19
5579 MOD_SEL1_18_17
5580 MOD_SEL1_16
5581 MOD_SEL1_15_14
5582 MOD_SEL1_13
5583 MOD_SEL1_12
5584 MOD_SEL1_11
5585 MOD_SEL1_10
5586 MOD_SEL1_9
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5587 /* RESERVED 8, 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5588 MOD_SEL1_6
5589 MOD_SEL1_5
5590 MOD_SEL1_4
5591 MOD_SEL1_3
5592 MOD_SEL1_2
5593 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5594 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5595 },
5596 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5597 GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
5598 -16, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5599 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5600 MOD_SEL2_31
5601 MOD_SEL2_30
5602 MOD_SEL2_29
5603 MOD_SEL2_28_27
5604 MOD_SEL2_26
5605 MOD_SEL2_25_24_23
5606 /* RESERVED 22 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5607 MOD_SEL2_21
5608 MOD_SEL2_20
5609 MOD_SEL2_19
5610 MOD_SEL2_18
5611 MOD_SEL2_17
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5612 /* RESERVED 16-1 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5613 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5614 },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5615 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5616};
5617
5618static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5619 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5620 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5621 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5622 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5623 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5624 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5625 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5626 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5627 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5628 } },
5629 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5630 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5631 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5632 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5633 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5634 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5635 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5636 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5637 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5638 } },
5639 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5640 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5641 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5642 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5643 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5644 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5645 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5646 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5647 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5648 } },
5649 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5650 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5651 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5652 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5653 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5654 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5655 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5656 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5657 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5658 } },
5659 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5660 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5661 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5662 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5663 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5664 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5665 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5666 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5667 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5668 } },
5669 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5670 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5671 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5672 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5673 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5674 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5675 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5676 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5677 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5678 } },
5679 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5680 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5681 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5682 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5683 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5684 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5685 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5686 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5687 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5688 } },
5689 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5690 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5691 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5692 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5693 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5694 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5695 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5696 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5697 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5698 } },
5699 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5700 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5701 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5702 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5703 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5704 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5705 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5706 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5707 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5708 } },
5709 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5710 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5711 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5712 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5713 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5714 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5715 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5716 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5717 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5718 } },
5719 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5720 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5721 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5722 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5723 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5724 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5725 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5726 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5727 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5728 } },
5729 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5730 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5731 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5732 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5733 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5734 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5735 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5736 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5737 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5738 } },
5739 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5740#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5741 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5742#endif
5743 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5744 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5745 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5746 } },
5747 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5748 { PIN_TDO, 28, 2 }, /* TDO */
5749 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5750 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5751 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5752 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5753 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5754 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5755 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5756 } },
5757 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5758 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5759 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5760 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5761 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5762 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5763 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5764 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5765 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5766 } },
5767 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5768 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5769 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5770 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5771 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5772 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5773 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5774 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5775 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5776 } },
5777 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5778 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5779 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5780 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5781 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5782 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5783 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5784 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5785 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5786 } },
5787 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5788 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5789 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5790 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5791 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5792 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5793 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5794 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5795 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5796 } },
5797 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5798 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5799 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5800 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5801 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5802 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5803 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5804 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5805 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5806 } },
5807 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5808 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5809 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5810 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5811 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5812 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5813 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5814 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5815 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5816 } },
5817 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5818 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5819 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5820 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5821 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5822 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5823 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5824 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5825 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5826 } },
5827 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5828 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5829 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5830 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5831 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5832 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5833 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5834 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5835 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5836 } },
5837 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5838 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5839 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5840 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5841 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5842 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5843 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5844 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5845 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5846 } },
5847 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5848 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5849 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5850 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5851 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5852 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5853 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5854 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5855 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5856 } },
5857 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5858 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5859 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5860 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5861 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5862 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5863 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
5864 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5865 } },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5866 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5867};
5868
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5869enum ioctrl_regs {
5870 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5871 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5872};
5873
5874static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5875 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5876 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5877 { /* sentinel */ }
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5878};
5879
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5880static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5881{
5882 int bit = -EINVAL;
5883
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5884 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5885
5886 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5887 bit = pin & 0x1f;
5888
5889 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5890 bit = (pin & 0x1f) + 12;
5891
5892 return bit;
5893}
5894
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5895static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5896 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5897 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5898 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5899 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5900 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5901 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5902 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5903 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5904 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5905 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5906 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5907 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5908 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5909 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5910 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5911 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5912 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5913 [16] = PIN_AVB_RXC, /* AVB_RXC */
5914 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5915 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5916 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5917 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5918 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5919 [22] = PIN_AVB_TXC, /* AVB_TXC */
5920 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5921 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5922 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5923 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5924 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5925 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5926 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5927 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5928 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5929 } },
5930 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5931 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5932 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5933 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5934 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5935 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5936 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5937 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5938 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5939 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5940 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5941 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5942 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5943 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5944 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5945 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5946 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5947 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5948 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5949 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5950 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5951 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5952 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5953 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5954 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5955 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5956 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5957 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5958 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5959 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5960 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5961 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5962 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5963 } },
5964 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5965 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5966 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5967 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5968 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5969 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5970 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5971 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5972 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5973 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5974 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5975 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5976 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5977 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5978 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5979 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5980 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5981 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5982 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5983 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5984 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5985 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5986 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5987 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5988 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5989 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5990 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5991 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5992 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5993 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5994 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5995 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5996 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5997 } },
5998 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5999 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
6000 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6001 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
6002 [ 3] = PIN_EXTALR, /* EXTALR*/
6003 [ 4] = PIN_TRST_N, /* TRST# */
6004 [ 5] = PIN_TCK, /* TCK */
6005 [ 6] = PIN_TMS, /* TMS */
6006 [ 7] = PIN_TDI, /* TDI */
6007 [ 8] = SH_PFC_PIN_NONE,
6008 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6009 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6010 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6011 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6012 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6013 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6014 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6015 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6016 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6017 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6018 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6019 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6020 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6021 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6022 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6023 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6024 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6025 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6026 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6027 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6028 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6029 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6030 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6031 } },
6032 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6033 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6034 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6035 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6036 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6037 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6038 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6039 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6040 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6041 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6042 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6043 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6044 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6045 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6046 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6047 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6048 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6049 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6050 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6051 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6052 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6053 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6054 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6055 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6056 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6057 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6058 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6059 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6060 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6061 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6062 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6063 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6064 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6065 } },
6066 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6067 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6068 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6069 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6070 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6071 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6072 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6073 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6074 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6075 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6076 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6077 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6078 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6079 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6080 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6081 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6082 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6083 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6084 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6085 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6086 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6087 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6088 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6089 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6090 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6091 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6092 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6093 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6094 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6095 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6096 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6097 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6098 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6099 } },
6100 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6101 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6102 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6103 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6104 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6105 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6106 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6107 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6108 [ 7] = SH_PFC_PIN_NONE,
6109 [ 8] = SH_PFC_PIN_NONE,
6110 [ 9] = SH_PFC_PIN_NONE,
6111 [10] = SH_PFC_PIN_NONE,
6112 [11] = SH_PFC_PIN_NONE,
6113 [12] = SH_PFC_PIN_NONE,
6114 [13] = SH_PFC_PIN_NONE,
6115 [14] = SH_PFC_PIN_NONE,
6116 [15] = SH_PFC_PIN_NONE,
6117 [16] = SH_PFC_PIN_NONE,
6118 [17] = SH_PFC_PIN_NONE,
6119 [18] = SH_PFC_PIN_NONE,
6120 [19] = SH_PFC_PIN_NONE,
6121 [20] = SH_PFC_PIN_NONE,
6122 [21] = SH_PFC_PIN_NONE,
6123 [22] = SH_PFC_PIN_NONE,
6124 [23] = SH_PFC_PIN_NONE,
6125 [24] = SH_PFC_PIN_NONE,
6126 [25] = SH_PFC_PIN_NONE,
6127 [26] = SH_PFC_PIN_NONE,
6128 [27] = SH_PFC_PIN_NONE,
6129 [28] = SH_PFC_PIN_NONE,
6130 [29] = SH_PFC_PIN_NONE,
6131 [30] = SH_PFC_PIN_NONE,
6132 [31] = SH_PFC_PIN_NONE,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6133 } },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]6134 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6135};
6136
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6137static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6138 .pin_to_pocctrl = r8a77951_pin_to_pocctrl,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6139 .get_bias = rcar_pinmux_get_bias,
6140 .set_bias = rcar_pinmux_set_bias,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6141};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6142
6143#ifdef CONFIG_PINCTRL_PFC_R8A774E1
6144const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
6145 .name = "r8a774e1_pfc",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6146 .ops = &r8a77951_pfc_ops,
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6147 .unlock_reg = 0xe6060000, /* PMMR */
6148
6149 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6150
6151 .pins = pinmux_pins,
6152 .nr_pins = ARRAY_SIZE(pinmux_pins),
6153 .groups = pinmux_groups.common,
6154 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6155 .functions = pinmux_functions.common,
6156 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6157
6158 .cfg_regs = pinmux_config_regs,
6159 .drive_regs = pinmux_drive_regs,
6160 .bias_regs = pinmux_bias_regs,
6161 .ioctrl_regs = pinmux_ioctrl_regs,
6162
6163 .pinmux_data = pinmux_data,
6164 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6165};
6166#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6167
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6168#ifdef CONFIG_PINCTRL_PFC_R8A77951
6169const struct sh_pfc_soc_info r8a77951_pinmux_info = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6170 .name = "r8a77951_pfc",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6171 .ops = &r8a77951_pfc_ops,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6172 .unlock_reg = 0xe6060000, /* PMMR */
6173
6174 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6175
6176 .pins = pinmux_pins,
6177 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6178 .groups = pinmux_groups.common,
6179 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6180 ARRAY_SIZE(pinmux_groups.automotive),
6181 .functions = pinmux_functions.common,
6182 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6183 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6184
6185 .cfg_regs = pinmux_config_regs,
6186 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6187 .bias_regs = pinmux_bias_regs,
6188 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6189
6190 .pinmux_data = pinmux_data,
6191 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6192};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6193#endif