blob: 4c662640a92067f8a3b7310f3c10dfa3df45973c [file] [log] [blame]
Simon Glassc036ebd2021-02-06 14:23:35 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <log.h>
9#include <tpm_api.h>
10#include <tpm-v1.h>
11#include <tpm-v2.h>
12#include <tpm_api.h>
13
14static bool is_tpm1(struct udevice *dev)
15{
16 return IS_ENABLED(CONFIG_TPM_V1) && tpm_get_version(dev) == TPM_V1;
17}
18
Simon Glass1f1eb342021-02-06 14:23:37 -070019static bool is_tpm2(struct udevice *dev)
20{
21 return IS_ENABLED(CONFIG_TPM_V2) && tpm_get_version(dev) == TPM_V2;
22}
23
Simon Glassc036ebd2021-02-06 14:23:35 -070024u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode)
25{
Simon Glass1f1eb342021-02-06 14:23:37 -070026 if (is_tpm1(dev)) {
Simon Glassc036ebd2021-02-06 14:23:35 -070027 return tpm1_startup(dev, mode);
Simon Glass1f1eb342021-02-06 14:23:37 -070028 } else if (is_tpm2(dev)) {
29 enum tpm2_startup_types type;
30
31 switch (mode) {
32 case TPM_ST_CLEAR:
33 type = TPM2_SU_CLEAR;
34 break;
35 case TPM_ST_STATE:
36 type = TPM2_SU_STATE;
37 break;
38 default:
39 case TPM_ST_DEACTIVATED:
40 return -EINVAL;
41 }
42 return tpm2_startup(dev, type);
43 } else {
Simon Glassc036ebd2021-02-06 14:23:35 -070044 return -ENOSYS;
Simon Glass1f1eb342021-02-06 14:23:37 -070045 }
Simon Glassc036ebd2021-02-06 14:23:35 -070046}
47
48u32 tpm_resume(struct udevice *dev)
49{
50 if (is_tpm1(dev))
51 return tpm1_startup(dev, TPM_ST_STATE);
Simon Glass1f1eb342021-02-06 14:23:37 -070052 else if (is_tpm2(dev))
53 return tpm2_startup(dev, TPM2_SU_STATE);
Simon Glassc036ebd2021-02-06 14:23:35 -070054 else
55 return -ENOSYS;
56}
57
58u32 tpm_self_test_full(struct udevice *dev)
59{
60 if (is_tpm1(dev))
61 return tpm1_self_test_full(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -070062 else if (is_tpm2(dev))
63 return tpm2_self_test(dev, TPMI_YES);
Simon Glassc036ebd2021-02-06 14:23:35 -070064 else
65 return -ENOSYS;
66}
67
68u32 tpm_continue_self_test(struct udevice *dev)
69{
70 if (is_tpm1(dev))
71 return tpm1_continue_self_test(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -070072 else if (is_tpm2(dev))
73 return tpm2_self_test(dev, TPMI_NO);
Simon Glassc036ebd2021-02-06 14:23:35 -070074 else
75 return -ENOSYS;
76}
77
78u32 tpm_clear_and_reenable(struct udevice *dev)
79{
80 u32 ret;
81
82 log_info("TPM: Clear and re-enable\n");
83 ret = tpm_force_clear(dev);
84 if (ret != TPM_SUCCESS) {
85 log_err("Can't initiate a force clear\n");
86 return ret;
87 }
88
89 if (is_tpm1(dev)) {
90 ret = tpm1_physical_enable(dev);
91 if (ret != TPM_SUCCESS) {
92 log_err("TPM: Can't set enabled state\n");
93 return ret;
94 }
95
96 ret = tpm1_physical_set_deactivated(dev, 0);
97 if (ret != TPM_SUCCESS) {
98 log_err("TPM: Can't set deactivated state\n");
99 return ret;
100 }
Simon Glassc036ebd2021-02-06 14:23:35 -0700101 }
102
103 return TPM_SUCCESS;
104}
105
106u32 tpm_nv_enable_locking(struct udevice *dev)
107{
108 if (is_tpm1(dev))
109 return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0);
Simon Glass1f1eb342021-02-06 14:23:37 -0700110 else if (is_tpm2(dev))
111 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700112 else
113 return -ENOSYS;
114}
115
116u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count)
117{
118 if (is_tpm1(dev))
119 return tpm1_nv_read_value(dev, index, data, count);
Simon Glass1f1eb342021-02-06 14:23:37 -0700120 else if (is_tpm2(dev))
Simon Glass3d930ed2021-02-06 14:23:40 -0700121 return tpm2_nv_read_value(dev, index, data, count);
Simon Glassc036ebd2021-02-06 14:23:35 -0700122 else
123 return -ENOSYS;
124}
125
126u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data,
127 u32 count)
128{
129 if (is_tpm1(dev))
130 return tpm1_nv_write_value(dev, index, data, count);
Simon Glass1f1eb342021-02-06 14:23:37 -0700131 else if (is_tpm2(dev))
Simon Glass3d930ed2021-02-06 14:23:40 -0700132 return tpm2_nv_write_value(dev, index, data, count);
Simon Glassc036ebd2021-02-06 14:23:35 -0700133 else
134 return -ENOSYS;
135}
136
137u32 tpm_set_global_lock(struct udevice *dev)
138{
139 return tpm_nv_write_value(dev, TPM_NV_INDEX_0, NULL, 0);
140}
141
142u32 tpm_write_lock(struct udevice *dev, u32 index)
143{
144 if (is_tpm1(dev))
145 return -ENOSYS;
Simon Glass1f1eb342021-02-06 14:23:37 -0700146 else if (is_tpm2(dev))
Simon Glasse9d3d592021-02-06 14:23:41 -0700147 return tpm2_write_lock(dev, index);
Simon Glassc036ebd2021-02-06 14:23:35 -0700148 else
149 return -ENOSYS;
150}
151
152u32 tpm_pcr_extend(struct udevice *dev, u32 index, const void *in_digest,
153 void *out_digest)
154{
155 if (is_tpm1(dev))
156 return tpm1_extend(dev, index, in_digest, out_digest);
Simon Glass1f1eb342021-02-06 14:23:37 -0700157 else if (is_tpm2(dev))
158 return tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, in_digest,
159 TPM2_DIGEST_LEN);
Simon Glassc036ebd2021-02-06 14:23:35 -0700160 else
161 return -ENOSYS;
162}
163
164u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count)
165{
166 if (is_tpm1(dev))
167 return tpm1_pcr_read(dev, index, data, count);
Simon Glass1f1eb342021-02-06 14:23:37 -0700168 else if (is_tpm2(dev))
169 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700170 else
171 return -ENOSYS;
172}
173
174u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence)
175{
176 if (is_tpm1(dev))
177 return tpm1_tsc_physical_presence(dev, presence);
Simon Glass1f1eb342021-02-06 14:23:37 -0700178
179 /*
180 * Nothing to do on TPM2 for this; use platform hierarchy availability
181 * instead.
182 */
183 else if (is_tpm2(dev))
184 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700185 else
186 return -ENOSYS;
187}
188
189u32 tpm_finalise_physical_presence(struct udevice *dev)
190{
191 if (is_tpm1(dev))
192 return tpm1_finalise_physical_presence(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -0700193
194 /* Nothing needs to be done with tpm2 */
195 else if (is_tpm2(dev))
196 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700197 else
198 return -ENOSYS;
199}
200
201u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count)
202{
203 if (is_tpm1(dev))
204 return tpm1_read_pubek(dev, data, count);
Simon Glass1f1eb342021-02-06 14:23:37 -0700205 else if (is_tpm2(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700206 return -ENOSYS; /* not implemented yet */
Simon Glass1f1eb342021-02-06 14:23:37 -0700207 else
208 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700209}
210
211u32 tpm_force_clear(struct udevice *dev)
212{
213 if (is_tpm1(dev))
214 return tpm1_force_clear(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -0700215 else if (is_tpm2(dev))
216 return tpm2_clear(dev, TPM2_RH_PLATFORM, NULL, 0);
Simon Glassc036ebd2021-02-06 14:23:35 -0700217 else
218 return -ENOSYS;
219}
220
221u32 tpm_physical_enable(struct udevice *dev)
222{
223 if (is_tpm1(dev))
224 return tpm1_physical_enable(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -0700225
226 /* Nothing needs to be done with tpm2 */
227 else if (is_tpm2(dev))
228 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700229 else
230 return -ENOSYS;
231}
232
233u32 tpm_physical_disable(struct udevice *dev)
234{
235 if (is_tpm1(dev))
236 return tpm1_physical_disable(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -0700237
238 /* Nothing needs to be done with tpm2 */
239 else if (is_tpm2(dev))
240 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700241 else
242 return -ENOSYS;
243}
244
245u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state)
246{
247 if (is_tpm1(dev))
248 return tpm1_physical_set_deactivated(dev, state);
Simon Glass1f1eb342021-02-06 14:23:37 -0700249 /* Nothing needs to be done with tpm2 */
250 else if (is_tpm2(dev))
251 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700252 else
253 return -ENOSYS;
254}
255
256u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap,
257 void *cap, size_t count)
258{
259 if (is_tpm1(dev))
260 return tpm1_get_capability(dev, cap_area, sub_cap, cap, count);
Simon Glass1f1eb342021-02-06 14:23:37 -0700261 else if (is_tpm2(dev))
262 return tpm2_get_capability(dev, cap_area, sub_cap, cap, count);
Simon Glassc036ebd2021-02-06 14:23:35 -0700263 else
264 return -ENOSYS;
265}
266
267u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm)
268{
269 if (is_tpm1(dev))
270 return tpm1_get_permissions(dev, index, perm);
Simon Glass1f1eb342021-02-06 14:23:37 -0700271 else if (is_tpm2(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700272 return -ENOSYS; /* not implemented yet */
Simon Glass1f1eb342021-02-06 14:23:37 -0700273 else
274 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700275}
276
277u32 tpm_get_random(struct udevice *dev, void *data, u32 count)
278{
279 if (is_tpm1(dev))
280 return tpm1_get_random(dev, data, count);
Simon Glass1f1eb342021-02-06 14:23:37 -0700281 else if (is_tpm2(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700282 return -ENOSYS; /* not implemented yet */
Simon Glass1f1eb342021-02-06 14:23:37 -0700283 else
284 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700285}