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git01.mediatek.com / filogic / uboot / 3d5ce4e5c71639e461ef4c5edd7c99287c269d69 / . / arch / arm / dts / ast2600.dtsi
blob: 98840ce7b0b3e743b09c0e5834c840dd8499d17e [file] [log] [blame]
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
116 fmc: flash-controller@1e620000 {
117 reg = < 0x1e620000 0xc4
118 0x20000000 0x10000000 >;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "aspeed,ast2600-fmc";
122 status = "disabled";
123 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&scu ASPEED_CLK_AHB>;
125 num-cs = <3>;
126 flash@0 {
127 reg = < 0 >;
128 compatible = "jedec,spi-nor";
129 status = "disabled";
130 };
131 flash@1 {
132 reg = < 1 >;
133 compatible = "jedec,spi-nor";
134 status = "disabled";
135 };
136 flash@2 {
137 reg = < 2 >;
138 compatible = "jedec,spi-nor";
139 status = "disabled";
140 };
141 };
142
143 spi1: flash-controller@1e630000 {
144 reg = < 0x1e630000 0xc4
145 0x30000000 0x08000000 >;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "aspeed,ast2600-spi";
149 clocks = <&scu ASPEED_CLK_AHB>;
150 num-cs = <2>;
151 status = "disabled";
152 flash@0 {
153 reg = < 0 >;
154 compatible = "jedec,spi-nor";
155 status = "disabled";
156 };
157 flash@1 {
158 reg = < 1 >;
159 compatible = "jedec,spi-nor";
160 status = "disabled";
161 };
162 };
163
164 spi2: flash-controller@1e631000 {
165 reg = < 0x1e631000 0xc4
166 0x50000000 0x08000000 >;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "aspeed,ast2600-spi";
170 clocks = <&scu ASPEED_CLK_AHB>;
171 num-cs = <3>;
172 status = "disabled";
173 flash@0 {
174 reg = < 0 >;
175 compatible = "jedec,spi-nor";
176 status = "disabled";
177 };
178 flash@1 {
179 reg = < 1 >;
180 compatible = "jedec,spi-nor";
181 status = "disabled";
182 };
183 flash@2 {
184 reg = < 2 >;
185 compatible = "jedec,spi-nor";
186 status = "disabled";
187 };
188 };
189
Joel Stanleyd18ef4f2021-10-27 14:17:28 +0800[diff] [blame]190 hace: hace@1e6d0000 {
191 compatible = "aspeed,ast2600-hace";
192 reg = <0x1e6d0000 0x200>;
193 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&scu ASPEED_CLK_GATE_YCLK>;
195 status = "disabled";
196 };
197
Chia-Wei Wang3435a3f2021-10-27 14:17:31 +0800[diff] [blame]198 acry: acry@1e6fa000 {
199 compatible = "aspeed,ast2600-acry";
200 reg = <0x1e6fa000 0x1000>,
201 <0x1e710000 0x10000>;
202 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
204 status = "disabled";
205 };
206
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]207 edac: sdram@1e6e0000 {
208 compatible = "aspeed,ast2600-sdram-edac";
209 reg = <0x1e6e0000 0x174>;
210 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
211 };
212
Dylan Hung82f25842021-12-09 10:12:26 +0800[diff] [blame]213 mdio: bus@1e650000 {
214 compatible = "simple-bus";
215 #address-cells = <1>;
216 #size-cells = <1>;
217 ranges = <0 0x1e650000 0x100>;
218
219 mdio0: mdio@0 {
220 compatible = "aspeed,ast2600-mdio";
221 reg = <0 0x8>;
222 resets = <&rst ASPEED_RESET_MII>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_mdio1_default>;
225 status = "disabled";
226 };
227
228 mdio1: mdio@8 {
229 compatible = "aspeed,ast2600-mdio";
230 reg = <0x8 0x8>;
231 resets = <&rst ASPEED_RESET_MII>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_mdio2_default>;
234 status = "disabled";
235 };
236
237 mdio2: mdio@10 {
238 compatible = "aspeed,ast2600-mdio";
239 reg = <0x10 0x8>;
240 resets = <&rst ASPEED_RESET_MII>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_mdio3_default>;
243 status = "disabled";
244 };
245
246 mdio3: mdio@18 {
247 compatible = "aspeed,ast2600-mdio";
248 reg = <0x18 0x8>;
249 resets = <&rst ASPEED_RESET_MII>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_mdio4_default>;
252 status = "disabled";
253 };
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]254 };
255
256 mac0: ftgmac@1e660000 {
257 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
258 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
259 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
261 status = "disabled";
262 };
263
264 mac1: ftgmac@1e680000 {
265 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
266 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
271 status = "disabled";
272 };
273
274 mac2: ftgmac@1e670000 {
275 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
276 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
281 status = "disabled";
282 };
283
284 mac3: ftgmac@1e690000 {
285 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
286 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
291 status = "disabled";
292 };
293
294 ehci0: usb@1e6a1000 {
295 compatible = "aspeed,aspeed-ehci", "usb-ehci";
296 reg = <0x1e6a1000 0x100>;
297 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_usb2ah_default>;
301 status = "disabled";
302 };
303
304 ehci1: usb@1e6a3000 {
305 compatible = "aspeed,aspeed-ehci", "usb-ehci";
306 reg = <0x1e6a3000 0x100>;
307 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_usb2bh_default>;
311 status = "disabled";
312 };
313
314 apb {
315 compatible = "simple-bus";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges;
319
320 syscon: syscon@1e6e2000 {
321 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
322 reg = <0x1e6e2000 0x1000>;
323 #address-cells = <1>;
324 #size-cells = <1>;
325 #clock-cells = <1>;
326 #reset-cells = <1>;
327 ranges = <0 0x1e6e2000 0x1000>;
328
329 pinctrl: pinctrl {
330 compatible = "aspeed,g6-pinctrl";
331 aspeed,external-nodes = <&gfx &lhc>;
332
333 };
334
335 vga_scratch: scratch {
336 compatible = "aspeed,bmc-misc";
337 };
338
339 scu_ic0: interrupt-controller@0 {
340 #interrupt-cells = <1>;
341 compatible = "aspeed,ast2600-scu-ic";
342 reg = <0x560 0x10>;
343 interrupt-parent = <&gic>;
344 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-controller;
346 };
347
348 scu_ic1: interrupt-controller@1 {
349 #interrupt-cells = <1>;
350 compatible = "aspeed,ast2600-scu-ic";
351 reg = <0x570 0x10>;
352 interrupt-parent = <&gic>;
353 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
354 interrupt-controller;
355 };
356
357 };
358
359 smp-memram@0 {
360 compatible = "aspeed,ast2600-smpmem", "syscon";
361 reg = <0x1e6e2180 0x40>;
362 };
363
364 gfx: display@1e6e6000 {
365 compatible = "aspeed,ast2500-gfx", "syscon";
366 reg = <0x1e6e6000 0x1000>;
367 reg-io-width = <4>;
368 };
369
370 pcie_bridge0: pcie@1e6ed000 {
371 compatible = "aspeed,ast2600-pcie";
372 #address-cells = <3>;
373 #size-cells = <2>;
374 reg = <0x1e6ed000 0x100>;
375 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
376 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
377 device_type = "pci";
378 bus-range = <0x00 0xff>;
379 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
380 cfg-handle = <&pcie_cfg0>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_pcie0rc_default>;
383
384 status = "disabled";
385 };
386
387 pcie_bridge1: pcie@1e6ed200 {
388 compatible = "aspeed,ast2600-pcie";
389 #address-cells = <3>;
390 #size-cells = <2>;
391 reg = <0x1e6ed200 0x100>;
392 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
393 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
394 device_type = "pci";
395 bus-range = <0x00 0xff>;
396 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
397 cfg-handle = <&pcie_cfg1>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_pcie1rc_default>;
400
401 status = "disabled";
402 };
403
404 sdhci: sdhci@1e740000 {
405 #interrupt-cells = <1>;
406 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
407 reg = <0x1e740000 0x1000>;
408 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-controller;
410 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
411 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
412 clock-names = "ctrlclk", "extclk";
413 #address-cells = <1>;
414 #size-cells = <1>;
415 ranges = <0x0 0x1e740000 0x1000>;
416
417 sdhci_slot0: sdhci_slot0@100 {
418 compatible = "aspeed,sdhci-ast2600";
419 reg = <0x100 0x100>;
420 interrupts = <0>;
421 interrupt-parent = <&sdhci>;
422 sdhci,auto-cmd12;
423 clocks = <&scu ASPEED_CLK_SDIO>;
424 status = "disabled";
425 };
426
427 sdhci_slot1: sdhci_slot1@200 {
428 compatible = "aspeed,sdhci-ast2600";
429 reg = <0x200 0x100>;
430 interrupts = <1>;
431 interrupt-parent = <&sdhci>;
432 sdhci,auto-cmd12;
433 clocks = <&scu ASPEED_CLK_SDIO>;
434 status = "disabled";
435 };
436 };
437
438 emmc: emmc@1e750000 {
439 #interrupt-cells = <1>;
440 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
441 reg = <0x1e750000 0x1000>;
442 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-controller;
444 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
445 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
446 clock-names = "ctrlclk", "extclk";
447 #address-cells = <1>;
448 #size-cells = <1>;
449 ranges = <0x0 0x1e750000 0x1000>;
450
451 emmc_slot0: emmc_slot0@100 {
452 compatible = "aspeed,emmc-ast2600";
453 reg = <0x100 0x100>;
454 interrupts = <0>;
455 interrupt-parent = <&emmc>;
456 clocks = <&scu ASPEED_CLK_EMMC>;
457 status = "disabled";
458 };
459 };
460
461 h2x: h2x@1e770000 {
462 compatible = "aspeed,ast2600-h2x";
463 reg = <0x1e770000 0x100>;
464 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
465 resets = <&rst ASPEED_RESET_H2X>;
466 #address-cells = <1>;
467 #size-cells = <1>;
468 ranges = <0x0 0x1e770000 0x100>;
469
470 status = "disabled";
471
472 pcie_cfg0: cfg0@80 {
473 reg = <0x80 0x80>;
474 compatible = "aspeed,ast2600-pcie-cfg";
475 };
476
477 pcie_cfg1: cfg1@C0 {
478 compatible = "aspeed,ast2600-pcie-cfg";
479 reg = <0xC0 0x80>;
480 };
481 };
482
483 gpio0: gpio@1e780000 {
484 compatible = "aspeed,ast2600-gpio";
485 reg = <0x1e780000 0x1000>;
486 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
487 #gpio-cells = <2>;
488 gpio-controller;
489 interrupt-controller;
490 gpio-ranges = <&pinctrl 0 0 220>;
491 ngpios = <208>;
492 };
493
494 gpio1: gpio@1e780800 {
495 compatible = "aspeed,ast2600-gpio";
496 reg = <0x1e780800 0x800>;
497 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
498 #gpio-cells = <2>;
499 gpio-controller;
500 interrupt-controller;
501 gpio-ranges = <&pinctrl 0 0 208>;
502 ngpios = <36>;
503 };
504
505 uart1: serial@1e783000 {
506 compatible = "ns16550a";
507 reg = <0x1e783000 0x20>;
508 reg-shift = <2>;
509 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
511 clock-frequency = <1846154>;
512 no-loopback-test;
513 status = "disabled";
514 };
515
516 uart5: serial@1e784000 {
517 compatible = "ns16550a";
518 reg = <0x1e784000 0x1000>;
519 reg-shift = <2>;
520 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
522 clock-frequency = <1846154>;
523 no-loopback-test;
524 status = "disabled";
525 };
526
527 wdt1: watchdog@1e785000 {
528 compatible = "aspeed,ast2600-wdt";
529 reg = <0x1e785000 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]530 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]531 };
532
533 wdt2: watchdog@1e785040 {
534 compatible = "aspeed,ast2600-wdt";
535 reg = <0x1e785040 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]536 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]537 };
538
539 wdt3: watchdog@1e785080 {
540 compatible = "aspeed,ast2600-wdt";
541 reg = <0x1e785080 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]542 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]543 };
544
545 wdt4: watchdog@1e7850C0 {
546 compatible = "aspeed,ast2600-wdt";
547 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]548 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]549 };
550
551 lpc: lpc@1e789000 {
552 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
553 reg = <0x1e789000 0x1000>;
554
555 #address-cells = <1>;
556 #size-cells = <1>;
557 ranges = <0x0 0x1e789000 0x1000>;
558
559 kcs1: kcs1@0 {
560 compatible = "aspeed,ast2600-kcs-bmc";
561 reg = <0x0 0x80>;
562 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
563 kcs_chan = <1>;
564 kcs_addr = <0xCA0>;
565 status = "disabled";
566 };
567
568 kcs2: kcs2@0 {
569 compatible = "aspeed,ast2600-kcs-bmc";
570 reg = <0x0 0x80>;
571 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
572 kcs_chan = <2>;
573 kcs_addr = <0xCA8>;
574 status = "disabled";
575 };
576
577 kcs3: kcs3@0 {
578 compatible = "aspeed,ast2600-kcs-bmc";
579 reg = <0x0 0x80>;
580 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
581 kcs_chan = <3>;
582 kcs_addr = <0xCA2>;
583 };
584
585 kcs4: kcs4@0 {
586 compatible = "aspeed,ast2600-kcs-bmc";
587 reg = <0x0 0x120>;
588 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
589 kcs_chan = <4>;
590 kcs_addr = <0xCA4>;
591 status = "disabled";
592 };
593
594 lpc_ctrl: lpc-ctrl@80 {
595 compatible = "aspeed,ast2600-lpc-ctrl";
596 reg = <0x80 0x80>;
597 status = "disabled";
598 };
599
600 lpc_snoop: lpc-snoop@80 {
601 compatible = "aspeed,ast2600-lpc-snoop";
602 reg = <0x80 0x80>;
603 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
604 status = "disabled";
605 };
606
607 lhc: lhc@a0 {
608 compatible = "aspeed,ast2600-lhc";
609 reg = <0xa0 0x24 0xc8 0x8>;
610 };
611
612 lpc_reset: reset-controller@98 {
613 compatible = "aspeed,ast2600-lpc-reset";
614 reg = <0x98 0x4>;
615 #reset-cells = <1>;
616 status = "disabled";
617 };
618
619 ibt: ibt@140 {
620 compatible = "aspeed,ast2600-ibt-bmc";
621 reg = <0x140 0x18>;
622 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
623 status = "disabled";
624 };
625
626 sio_regs: regs {
627 compatible = "aspeed,bmc-misc";
628 };
629
630 mbox: mbox@200 {
631 compatible = "aspeed,ast2600-mbox";
632 reg = <0x200 0x5c>;
633 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
634 #mbox-cells = <1>;
635 status = "disabled";
636 };
637 };
638
639 uart2: serial@1e78d000 {
640 compatible = "ns16550a";
641 reg = <0x1e78d000 0x20>;
642 reg-shift = <2>;
643 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
645 clock-frequency = <1846154>;
646 no-loopback-test;
647 status = "disabled";
648 };
649
650 uart3: serial@1e78e000 {
651 compatible = "ns16550a";
652 reg = <0x1e78e000 0x20>;
653 reg-shift = <2>;
654 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
656 clock-frequency = <1846154>;
657 no-loopback-test;
658 status = "disabled";
659 };
660
661 uart4: serial@1e78f000 {
662 compatible = "ns16550a";
663 reg = <0x1e78f000 0x20>;
664 reg-shift = <2>;
665 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
667 clock-frequency = <1846154>;
668 no-loopback-test;
669 status = "disabled";
670 };
671
672 i2c: bus@1e78a000 {
673 compatible = "simple-bus";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 ranges = <0 0x1e78a000 0x1000>;
677 };
678
679 fsim0: fsi@1e79b000 {
680 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
681 reg = <0x1e79b000 0x94>;
682 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_fsi1_default>;
685 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
686 status = "disabled";
687 };
688
689 fsim1: fsi@1e79b100 {
690 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
691 reg = <0x1e79b100 0x94>;
692 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_fsi2_default>;
695 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
696 status = "disabled";
697 };
698
699 uart6: serial@1e790000 {
700 compatible = "ns16550a";
701 reg = <0x1e790000 0x20>;
702 reg-shift = <2>;
703 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
705 clock-frequency = <1846154>;
706 no-loopback-test;
707 status = "disabled";
708 };
709
710 uart7: serial@1e790100 {
711 compatible = "ns16550a";
712 reg = <0x1e790100 0x20>;
713 reg-shift = <2>;
714 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
716 clock-frequency = <1846154>;
717 no-loopback-test;
718 status = "disabled";
719 };
720
721 uart8: serial@1e790200 {
722 compatible = "ns16550a";
723 reg = <0x1e790200 0x20>;
724 reg-shift = <2>;
725 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
727 clock-frequency = <1846154>;
728 no-loopback-test;
729 status = "disabled";
730 };
731
732 uart9: serial@1e790300 {
733 compatible = "ns16550a";
734 reg = <0x1e790300 0x20>;
735 reg-shift = <2>;
736 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
738 clock-frequency = <1846154>;
739 no-loopback-test;
740 status = "disabled";
741 };
742
743 uart10: serial@1e790400 {
744 compatible = "ns16550a";
745 reg = <0x1e790400 0x20>;
746 reg-shift = <2>;
747 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
749 clock-frequency = <1846154>;
750 no-loopback-test;
751 status = "disabled";
752 };
753
754 uart11: serial@1e790500 {
755 compatible = "ns16550a";
756 reg = <0x1e790400 0x20>;
757 reg-shift = <2>;
758 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
760 clock-frequency = <1846154>;
761 no-loopback-test;
762 status = "disabled";
763 };
764
765 uart12: serial@1e790600 {
766 compatible = "ns16550a";
767 reg = <0x1e790600 0x20>;
768 reg-shift = <2>;
769 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
771 clock-frequency = <1846154>;
772 no-loopback-test;
773 status = "disabled";
774 };
775
776 uart13: serial@1e790700 {
777 compatible = "ns16550a";
778 reg = <0x1e790700 0x20>;
779 reg-shift = <2>;
780 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
782 clock-frequency = <1846154>;
783 no-loopback-test;
784 status = "disabled";
785 };
786
787 display_port: dp@1e6eb000 {
788 compatible = "aspeed,ast2600-displayport";
789 reg = <0x1e6eb000 0x200>;
790 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
791 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
792 status = "disabled";
793 };
794
795 };
796
797 };
798
799};
800
801&i2c {
802 i2cglobal: i2cg@00 {
803 compatible = "aspeed,ast2600-i2c-global";
804 reg = <0x0 0x40>;
805 resets = <&rst ASPEED_RESET_I2C>;
806#if 0
807 new-mode;
808#endif
809 };
810
811 i2c0: i2c@80 {
812 #address-cells = <1>;
813 #size-cells = <0>;
814 #interrupt-cells = <1>;
815
816 reg = <0x80 0x80 0xC00 0x20>;
817 compatible = "aspeed,ast2600-i2c-bus";
818 bus-frequency = <100000>;
819 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&scu ASPEED_CLK_APB2>;
821 status = "disabled";
822 };
823
824 i2c1: i2c@100 {
825 #address-cells = <1>;
826 #size-cells = <0>;
827 #interrupt-cells = <1>;
828
829 reg = <0x100 0x80 0xC20 0x20>;
830 compatible = "aspeed,ast2600-i2c-bus";
831 bus-frequency = <100000>;
832 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&scu ASPEED_CLK_APB2>;
834 status = "disabled";
835 };
836
837 i2c2: i2c@180 {
838 #address-cells = <1>;
839 #size-cells = <0>;
840 #interrupt-cells = <1>;
841
842 reg = <0x180 0x80 0xC40 0x20>;
843 compatible = "aspeed,ast2600-i2c-bus";
844 bus-frequency = <100000>;
845 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&scu ASPEED_CLK_APB2>;
847 };
848
849 i2c3: i2c@200 {
850 #address-cells = <1>;
851 #size-cells = <0>;
852 #interrupt-cells = <1>;
853
854 reg = <0x200 0x40 0xC60 0x20>;
855 compatible = "aspeed,ast2600-i2c-bus";
856 bus-frequency = <100000>;
857 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&scu ASPEED_CLK_APB2>;
859 };
860
861 i2c4: i2c@280 {
862 #address-cells = <1>;
863 #size-cells = <0>;
864 #interrupt-cells = <1>;
865
866 reg = <0x280 0x80 0xC80 0x20>;
867 compatible = "aspeed,ast2600-i2c-bus";
868 bus-frequency = <100000>;
869 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&scu ASPEED_CLK_APB2>;
871 };
872
873 i2c5: i2c@300 {
874 #address-cells = <1>;
875 #size-cells = <0>;
876 #interrupt-cells = <1>;
877
878 reg = <0x300 0x40 0xCA0 0x20>;
879 compatible = "aspeed,ast2600-i2c-bus";
880 bus-frequency = <100000>;
881 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&scu ASPEED_CLK_APB2>;
883 };
884
885 i2c6: i2c@380 {
886 #address-cells = <1>;
887 #size-cells = <0>;
888 #interrupt-cells = <1>;
889
890 reg = <0x380 0x80 0xCC0 0x20>;
891 compatible = "aspeed,ast2600-i2c-bus";
892 bus-frequency = <100000>;
893 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&scu ASPEED_CLK_APB2>;
895 };
896
897 i2c7: i2c@400 {
898 #address-cells = <1>;
899 #size-cells = <0>;
900 #interrupt-cells = <1>;
901
902 reg = <0x400 0x80 0xCE0 0x20>;
903 compatible = "aspeed,ast2600-i2c-bus";
904 bus-frequency = <100000>;
905 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&scu ASPEED_CLK_APB2>;
907 };
908
909 i2c8: i2c@480 {
910 #address-cells = <1>;
911 #size-cells = <0>;
912 #interrupt-cells = <1>;
913
914 reg = <0x480 0x80 0xD00 0x20>;
915 compatible = "aspeed,ast2600-i2c-bus";
916 bus-frequency = <100000>;
917 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&scu ASPEED_CLK_APB2>;
919 };
920
921 i2c9: i2c@500 {
922 #address-cells = <1>;
923 #size-cells = <0>;
924 #interrupt-cells = <1>;
925
926 reg = <0x500 0x80 0xD20 0x20>;
927 compatible = "aspeed,ast2600-i2c-bus";
928 bus-frequency = <100000>;
929 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&scu ASPEED_CLK_APB2>;
931 status = "disabled";
932 };
933
934 i2c10: i2c@580 {
935 #address-cells = <1>;
936 #size-cells = <0>;
937 #interrupt-cells = <1>;
938
939 reg = <0x580 0x80 0xD40 0x20>;
940 compatible = "aspeed,ast2600-i2c-bus";
941 bus-frequency = <100000>;
942 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&scu ASPEED_CLK_APB2>;
944 status = "disabled";
945 };
946
947 i2c11: i2c@600 {
948 #address-cells = <1>;
949 #size-cells = <0>;
950 #interrupt-cells = <1>;
951
952 reg = <0x600 0x80 0xD60 0x20>;
953 compatible = "aspeed,ast2600-i2c-bus";
954 bus-frequency = <100000>;
955 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&scu ASPEED_CLK_APB2>;
957 status = "disabled";
958 };
959
960 i2c12: i2c@680 {
961 #address-cells = <1>;
962 #size-cells = <0>;
963 #interrupt-cells = <1>;
964
965 reg = <0x680 0x80 0xD80 0x20>;
966 compatible = "aspeed,ast2600-i2c-bus";
967 bus-frequency = <100000>;
968 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&scu ASPEED_CLK_APB2>;
970 status = "disabled";
971 };
972
973 i2c13: i2c@700 {
974 #address-cells = <1>;
975 #size-cells = <0>;
976 #interrupt-cells = <1>;
977
978 reg = <0x700 0x80 0xDA0 0x20>;
979 compatible = "aspeed,ast2600-i2c-bus";
980 bus-frequency = <100000>;
981 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&scu ASPEED_CLK_APB2>;
983 status = "disabled";
984 };
985
986 i2c14: i2c@780 {
987 #address-cells = <1>;
988 #size-cells = <0>;
989 #interrupt-cells = <1>;
990
991 reg = <0x780 0x80 0xDC0 0x20>;
992 compatible = "aspeed,ast2600-i2c-bus";
993 bus-frequency = <100000>;
994 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&scu ASPEED_CLK_APB2>;
996 status = "disabled";
997 };
998
999 i2c15: i2c@800 {
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002 #interrupt-cells = <1>;
1003
1004 reg = <0x800 0x80 0xDE0 0x20>;
1005 compatible = "aspeed,ast2600-i2c-bus";
1006 bus-frequency = <100000>;
1007 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&scu ASPEED_CLK_APB2>;
1009 status = "disabled";
1010 };
1011
1012};
1013
1014&pinctrl {
1015 pinctrl_fmcquad_default: fmcquad_default {
1016 function = "FMCQUAD";
1017 groups = "FMCQUAD";
1018 };
1019
1020 pinctrl_spi1_default: spi1_default {
1021 function = "SPI1";
1022 groups = "SPI1";
1023 };
1024
1025 pinctrl_spi1abr_default: spi1abr_default {
1026 function = "SPI1ABR";
1027 groups = "SPI1ABR";
1028 };
1029
1030 pinctrl_spi1cs1_default: spi1cs1_default {
1031 function = "SPI1CS1";
1032 groups = "SPI1CS1";
1033 };
1034
1035 pinctrl_spi1wp_default: spi1wp_default {
1036 function = "SPI1WP";
1037 groups = "SPI1WP";
1038 };
1039
1040 pinctrl_spi1quad_default: spi1quad_default {
1041 function = "SPI1QUAD";
1042 groups = "SPI1QUAD";
1043 };
1044
1045 pinctrl_spi2_default: spi2_default {
1046 function = "SPI2";
1047 groups = "SPI2";
1048 };
1049
1050 pinctrl_spi2cs1_default: spi2cs1_default {
1051 function = "SPI2CS1";
1052 groups = "SPI2CS1";
1053 };
1054
1055 pinctrl_spi2cs2_default: spi2cs2_default {
1056 function = "SPI2CS2";
1057 groups = "SPI2CS2";
1058 };
1059
1060 pinctrl_spi2quad_default: spi2quad_default {
1061 function = "SPI2QUAD";
1062 groups = "SPI2QUAD";
1063 };
1064
1065 pinctrl_acpi_default: acpi_default {
1066 function = "ACPI";
1067 groups = "ACPI";
1068 };
1069
1070 pinctrl_adc0_default: adc0_default {
1071 function = "ADC0";
1072 groups = "ADC0";
1073 };
1074
1075 pinctrl_adc1_default: adc1_default {
1076 function = "ADC1";
1077 groups = "ADC1";
1078 };
1079
1080 pinctrl_adc10_default: adc10_default {
1081 function = "ADC10";
1082 groups = "ADC10";
1083 };
1084
1085 pinctrl_adc11_default: adc11_default {
1086 function = "ADC11";
1087 groups = "ADC11";
1088 };
1089
1090 pinctrl_adc12_default: adc12_default {
1091 function = "ADC12";
1092 groups = "ADC12";
1093 };
1094
1095 pinctrl_adc13_default: adc13_default {
1096 function = "ADC13";
1097 groups = "ADC13";
1098 };
1099
1100 pinctrl_adc14_default: adc14_default {
1101 function = "ADC14";
1102 groups = "ADC14";
1103 };
1104
1105 pinctrl_adc15_default: adc15_default {
1106 function = "ADC15";
1107 groups = "ADC15";
1108 };
1109
1110 pinctrl_adc2_default: adc2_default {
1111 function = "ADC2";
1112 groups = "ADC2";
1113 };
1114
1115 pinctrl_adc3_default: adc3_default {
1116 function = "ADC3";
1117 groups = "ADC3";
1118 };
1119
1120 pinctrl_adc4_default: adc4_default {
1121 function = "ADC4";
1122 groups = "ADC4";
1123 };
1124
1125 pinctrl_adc5_default: adc5_default {
1126 function = "ADC5";
1127 groups = "ADC5";
1128 };
1129
1130 pinctrl_adc6_default: adc6_default {
1131 function = "ADC6";
1132 groups = "ADC6";
1133 };
1134
1135 pinctrl_adc7_default: adc7_default {
1136 function = "ADC7";
1137 groups = "ADC7";
1138 };
1139
1140 pinctrl_adc8_default: adc8_default {
1141 function = "ADC8";
1142 groups = "ADC8";
1143 };
1144
1145 pinctrl_adc9_default: adc9_default {
1146 function = "ADC9";
1147 groups = "ADC9";
1148 };
1149
1150 pinctrl_bmcint_default: bmcint_default {
1151 function = "BMCINT";
1152 groups = "BMCINT";
1153 };
1154
1155 pinctrl_ddcclk_default: ddcclk_default {
1156 function = "DDCCLK";
1157 groups = "DDCCLK";
1158 };
1159
1160 pinctrl_ddcdat_default: ddcdat_default {
1161 function = "DDCDAT";
1162 groups = "DDCDAT";
1163 };
1164
1165 pinctrl_espi_default: espi_default {
1166 function = "ESPI";
1167 groups = "ESPI";
1168 };
1169
1170 pinctrl_fsi1_default: fsi1_default {
1171 function = "FSI1";
1172 groups = "FSI1";
1173 };
1174
1175 pinctrl_fsi2_default: fsi2_default {
1176 function = "FSI2";
1177 groups = "FSI2";
1178 };
1179
1180 pinctrl_fwspics1_default: fwspics1_default {
1181 function = "FWSPICS1";
1182 groups = "FWSPICS1";
1183 };
1184
1185 pinctrl_fwspics2_default: fwspics2_default {
1186 function = "FWSPICS2";
1187 groups = "FWSPICS2";
1188 };
1189
1190 pinctrl_gpid0_default: gpid0_default {
1191 function = "GPID0";
1192 groups = "GPID0";
1193 };
1194
1195 pinctrl_gpid2_default: gpid2_default {
1196 function = "GPID2";
1197 groups = "GPID2";
1198 };
1199
1200 pinctrl_gpid4_default: gpid4_default {
1201 function = "GPID4";
1202 groups = "GPID4";
1203 };
1204
1205 pinctrl_gpid6_default: gpid6_default {
1206 function = "GPID6";
1207 groups = "GPID6";
1208 };
1209
1210 pinctrl_gpie0_default: gpie0_default {
1211 function = "GPIE0";
1212 groups = "GPIE0";
1213 };
1214
1215 pinctrl_gpie2_default: gpie2_default {
1216 function = "GPIE2";
1217 groups = "GPIE2";
1218 };
1219
1220 pinctrl_gpie4_default: gpie4_default {
1221 function = "GPIE4";
1222 groups = "GPIE4";
1223 };
1224
1225 pinctrl_gpie6_default: gpie6_default {
1226 function = "GPIE6";
1227 groups = "GPIE6";
1228 };
1229
1230 pinctrl_i2c1_default: i2c1_default {
1231 function = "I2C1";
1232 groups = "I2C1";
1233 };
1234 pinctrl_i2c2_default: i2c2_default {
1235 function = "I2C2";
1236 groups = "I2C2";
1237 };
1238
1239 pinctrl_i2c3_default: i2c3_default {
1240 function = "I2C3";
1241 groups = "I2C3";
1242 };
1243
1244 pinctrl_i2c4_default: i2c4_default {
1245 function = "I2C4";
1246 groups = "I2C4";
1247 };
1248
1249 pinctrl_i2c5_default: i2c5_default {
1250 function = "I2C5";
1251 groups = "I2C5";
1252 };
1253
1254 pinctrl_i2c6_default: i2c6_default {
1255 function = "I2C6";
1256 groups = "I2C6";
1257 };
1258
1259 pinctrl_i2c7_default: i2c7_default {
1260 function = "I2C7";
1261 groups = "I2C7";
1262 };
1263
1264 pinctrl_i2c8_default: i2c8_default {
1265 function = "I2C8";
1266 groups = "I2C8";
1267 };
1268
1269 pinctrl_i2c9_default: i2c9_default {
1270 function = "I2C9";
1271 groups = "I2C9";
1272 };
1273
1274 pinctrl_i2c10_default: i2c10_default {
1275 function = "I2C10";
1276 groups = "I2C10";
1277 };
1278
1279 pinctrl_i2c11_default: i2c11_default {
1280 function = "I2C11";
1281 groups = "I2C11";
1282 };
1283
1284 pinctrl_i2c12_default: i2c12_default {
1285 function = "I2C12";
1286 groups = "I2C12";
1287 };
1288
1289 pinctrl_i2c13_default: i2c13_default {
1290 function = "I2C13";
1291 groups = "I2C13";
1292 };
1293
1294 pinctrl_i2c14_default: i2c14_default {
1295 function = "I2C14";
1296 groups = "I2C14";
1297 };
1298
1299 pinctrl_i2c15_default: i2c15_default {
1300 function = "I2C15";
1301 groups = "I2C15";
1302 };
1303
1304 pinctrl_i2c16_default: i2c16_default {
1305 function = "I2C16";
1306 groups = "I2C16";
1307 };
1308
1309 pinctrl_lad0_default: lad0_default {
1310 function = "LAD0";
1311 groups = "LAD0";
1312 };
1313
1314 pinctrl_lad1_default: lad1_default {
1315 function = "LAD1";
1316 groups = "LAD1";
1317 };
1318
1319 pinctrl_lad2_default: lad2_default {
1320 function = "LAD2";
1321 groups = "LAD2";
1322 };
1323
1324 pinctrl_lad3_default: lad3_default {
1325 function = "LAD3";
1326 groups = "LAD3";
1327 };
1328
1329 pinctrl_lclk_default: lclk_default {
1330 function = "LCLK";
1331 groups = "LCLK";
1332 };
1333
1334 pinctrl_lframe_default: lframe_default {
1335 function = "LFRAME";
1336 groups = "LFRAME";
1337 };
1338
1339 pinctrl_lpchc_default: lpchc_default {
1340 function = "LPCHC";
1341 groups = "LPCHC";
1342 };
1343
1344 pinctrl_lpcpd_default: lpcpd_default {
1345 function = "LPCPD";
1346 groups = "LPCPD";
1347 };
1348
1349 pinctrl_lpcplus_default: lpcplus_default {
1350 function = "LPCPLUS";
1351 groups = "LPCPLUS";
1352 };
1353
1354 pinctrl_lpcpme_default: lpcpme_default {
1355 function = "LPCPME";
1356 groups = "LPCPME";
1357 };
1358
1359 pinctrl_lpcrst_default: lpcrst_default {
1360 function = "LPCRST";
1361 groups = "LPCRST";
1362 };
1363
1364 pinctrl_lpcsmi_default: lpcsmi_default {
1365 function = "LPCSMI";
1366 groups = "LPCSMI";
1367 };
1368
1369 pinctrl_lsirq_default: lsirq_default {
1370 function = "LSIRQ";
1371 groups = "LSIRQ";
1372 };
1373
1374 pinctrl_mac1link_default: mac1link_default {
1375 function = "MAC1LINK";
1376 groups = "MAC1LINK";
1377 };
1378
1379 pinctrl_mac2link_default: mac2link_default {
1380 function = "MAC2LINK";
1381 groups = "MAC2LINK";
1382 };
1383
1384 pinctrl_mac3link_default: mac3link_default {
1385 function = "MAC3LINK";
1386 groups = "MAC3LINK";
1387 };
1388
1389 pinctrl_mac4link_default: mac4link_default {
1390 function = "MAC4LINK";
1391 groups = "MAC4LINK";
1392 };
1393
1394 pinctrl_mdio1_default: mdio1_default {
1395 function = "MDIO1";
1396 groups = "MDIO1";
1397 };
1398
1399 pinctrl_mdio2_default: mdio2_default {
1400 function = "MDIO2";
1401 groups = "MDIO2";
1402 };
1403
1404 pinctrl_mdio3_default: mdio3_default {
1405 function = "MDIO3";
1406 groups = "MDIO3";
1407 };
1408
1409 pinctrl_mdio4_default: mdio4_default {
1410 function = "MDIO4";
1411 groups = "MDIO4";
1412 };
1413
1414 pinctrl_rmii1_default: rmii1_default {
1415 function = "RMII1";
1416 groups = "RMII1";
1417 };
1418
1419 pinctrl_rmii2_default: rmii2_default {
1420 function = "RMII2";
1421 groups = "RMII2";
1422 };
1423
1424 pinctrl_rmii3_default: rmii3_default {
1425 function = "RMII3";
1426 groups = "RMII3";
1427 };
1428
1429 pinctrl_rmii4_default: rmii4_default {
1430 function = "RMII4";
1431 groups = "RMII4";
1432 };
1433
1434 pinctrl_rmii1rclk_default: rmii1rclk_default {
1435 function = "RMII1RCLK";
1436 groups = "RMII1RCLK";
1437 };
1438
1439 pinctrl_rmii2rclk_default: rmii2rclk_default {
1440 function = "RMII2RCLK";
1441 groups = "RMII2RCLK";
1442 };
1443
1444 pinctrl_rmii3rclk_default: rmii3rclk_default {
1445 function = "RMII3RCLK";
1446 groups = "RMII3RCLK";
1447 };
1448
1449 pinctrl_rmii4rclk_default: rmii4rclk_default {
1450 function = "RMII4RCLK";
1451 groups = "RMII4RCLK";
1452 };
1453
1454 pinctrl_ncts1_default: ncts1_default {
1455 function = "NCTS1";
1456 groups = "NCTS1";
1457 };
1458
1459 pinctrl_ncts2_default: ncts2_default {
1460 function = "NCTS2";
1461 groups = "NCTS2";
1462 };
1463
1464 pinctrl_ncts3_default: ncts3_default {
1465 function = "NCTS3";
1466 groups = "NCTS3";
1467 };
1468
1469 pinctrl_ncts4_default: ncts4_default {
1470 function = "NCTS4";
1471 groups = "NCTS4";
1472 };
1473
1474 pinctrl_ndcd1_default: ndcd1_default {
1475 function = "NDCD1";
1476 groups = "NDCD1";
1477 };
1478
1479 pinctrl_ndcd2_default: ndcd2_default {
1480 function = "NDCD2";
1481 groups = "NDCD2";
1482 };
1483
1484 pinctrl_ndcd3_default: ndcd3_default {
1485 function = "NDCD3";
1486 groups = "NDCD3";
1487 };
1488
1489 pinctrl_ndcd4_default: ndcd4_default {
1490 function = "NDCD4";
1491 groups = "NDCD4";
1492 };
1493
1494 pinctrl_ndsr1_default: ndsr1_default {
1495 function = "NDSR1";
1496 groups = "NDSR1";
1497 };
1498
1499 pinctrl_ndsr2_default: ndsr2_default {
1500 function = "NDSR2";
1501 groups = "NDSR2";
1502 };
1503
1504 pinctrl_ndsr3_default: ndsr3_default {
1505 function = "NDSR3";
1506 groups = "NDSR3";
1507 };
1508
1509 pinctrl_ndsr4_default: ndsr4_default {
1510 function = "NDSR4";
1511 groups = "NDSR4";
1512 };
1513
1514 pinctrl_ndtr1_default: ndtr1_default {
1515 function = "NDTR1";
1516 groups = "NDTR1";
1517 };
1518
1519 pinctrl_ndtr2_default: ndtr2_default {
1520 function = "NDTR2";
1521 groups = "NDTR2";
1522 };
1523
1524 pinctrl_ndtr3_default: ndtr3_default {
1525 function = "NDTR3";
1526 groups = "NDTR3";
1527 };
1528
1529 pinctrl_ndtr4_default: ndtr4_default {
1530 function = "NDTR4";
1531 groups = "NDTR4";
1532 };
1533
1534 pinctrl_nri1_default: nri1_default {
1535 function = "NRI1";
1536 groups = "NRI1";
1537 };
1538
1539 pinctrl_nri2_default: nri2_default {
1540 function = "NRI2";
1541 groups = "NRI2";
1542 };
1543
1544 pinctrl_nri3_default: nri3_default {
1545 function = "NRI3";
1546 groups = "NRI3";
1547 };
1548
1549 pinctrl_nri4_default: nri4_default {
1550 function = "NRI4";
1551 groups = "NRI4";
1552 };
1553
1554 pinctrl_nrts1_default: nrts1_default {
1555 function = "NRTS1";
1556 groups = "NRTS1";
1557 };
1558
1559 pinctrl_nrts2_default: nrts2_default {
1560 function = "NRTS2";
1561 groups = "NRTS2";
1562 };
1563
1564 pinctrl_nrts3_default: nrts3_default {
1565 function = "NRTS3";
1566 groups = "NRTS3";
1567 };
1568
1569 pinctrl_nrts4_default: nrts4_default {
1570 function = "NRTS4";
1571 groups = "NRTS4";
1572 };
1573
1574 pinctrl_oscclk_default: oscclk_default {
1575 function = "OSCCLK";
1576 groups = "OSCCLK";
1577 };
1578
1579 pinctrl_pewake_default: pewake_default {
1580 function = "PEWAKE";
1581 groups = "PEWAKE";
1582 };
1583
1584 pinctrl_pnor_default: pnor_default {
1585 function = "PNOR";
1586 groups = "PNOR";
1587 };
1588
1589 pinctrl_pwm0_default: pwm0_default {
1590 function = "PWM0";
1591 groups = "PWM0";
1592 };
1593
1594 pinctrl_pwm1_default: pwm1_default {
1595 function = "PWM1";
1596 groups = "PWM1";
1597 };
1598
1599 pinctrl_pwm2_default: pwm2_default {
1600 function = "PWM2";
1601 groups = "PWM2";
1602 };
1603
1604 pinctrl_pwm3_default: pwm3_default {
1605 function = "PWM3";
1606 groups = "PWM3";
1607 };
1608
1609 pinctrl_pwm4_default: pwm4_default {
1610 function = "PWM4";
1611 groups = "PWM4";
1612 };
1613
1614 pinctrl_pwm5_default: pwm5_default {
1615 function = "PWM5";
1616 groups = "PWM5";
1617 };
1618
1619 pinctrl_pwm6_default: pwm6_default {
1620 function = "PWM6";
1621 groups = "PWM6";
1622 };
1623
1624 pinctrl_pwm7_default: pwm7_default {
1625 function = "PWM7";
1626 groups = "PWM7";
1627 };
1628
1629 pinctrl_rgmii1_default: rgmii1_default {
1630 function = "RGMII1";
1631 groups = "RGMII1";
1632 };
1633
1634 pinctrl_rgmii2_default: rgmii2_default {
1635 function = "RGMII2";
1636 groups = "RGMII2";
1637 };
1638
1639 pinctrl_rgmii3_default: rgmii3_default {
1640 function = "RGMII3";
1641 groups = "RGMII3";
1642 };
1643
1644 pinctrl_rgmii4_default: rgmii4_default {
1645 function = "RGMII4";
1646 groups = "RGMII4";
1647 };
1648
1649 pinctrl_rmii1_default: rmii1_default {
1650 function = "RMII1";
1651 groups = "RMII1";
1652 };
1653
1654 pinctrl_rmii2_default: rmii2_default {
1655 function = "RMII2";
1656 groups = "RMII2";
1657 };
1658
1659 pinctrl_rxd1_default: rxd1_default {
1660 function = "RXD1";
1661 groups = "RXD1";
1662 };
1663
1664 pinctrl_rxd2_default: rxd2_default {
1665 function = "RXD2";
1666 groups = "RXD2";
1667 };
1668
1669 pinctrl_rxd3_default: rxd3_default {
1670 function = "RXD3";
1671 groups = "RXD3";
1672 };
1673
1674 pinctrl_rxd4_default: rxd4_default {
1675 function = "RXD4";
1676 groups = "RXD4";
1677 };
1678
1679 pinctrl_salt1_default: salt1_default {
1680 function = "SALT1";
1681 groups = "SALT1";
1682 };
1683
1684 pinctrl_salt10_default: salt10_default {
1685 function = "SALT10";
1686 groups = "SALT10";
1687 };
1688
1689 pinctrl_salt11_default: salt11_default {
1690 function = "SALT11";
1691 groups = "SALT11";
1692 };
1693
1694 pinctrl_salt12_default: salt12_default {
1695 function = "SALT12";
1696 groups = "SALT12";
1697 };
1698
1699 pinctrl_salt13_default: salt13_default {
1700 function = "SALT13";
1701 groups = "SALT13";
1702 };
1703
1704 pinctrl_salt14_default: salt14_default {
1705 function = "SALT14";
1706 groups = "SALT14";
1707 };
1708
1709 pinctrl_salt2_default: salt2_default {
1710 function = "SALT2";
1711 groups = "SALT2";
1712 };
1713
1714 pinctrl_salt3_default: salt3_default {
1715 function = "SALT3";
1716 groups = "SALT3";
1717 };
1718
1719 pinctrl_salt4_default: salt4_default {
1720 function = "SALT4";
1721 groups = "SALT4";
1722 };
1723
1724 pinctrl_salt5_default: salt5_default {
1725 function = "SALT5";
1726 groups = "SALT5";
1727 };
1728
1729 pinctrl_salt6_default: salt6_default {
1730 function = "SALT6";
1731 groups = "SALT6";
1732 };
1733
1734 pinctrl_salt7_default: salt7_default {
1735 function = "SALT7";
1736 groups = "SALT7";
1737 };
1738
1739 pinctrl_salt8_default: salt8_default {
1740 function = "SALT8";
1741 groups = "SALT8";
1742 };
1743
1744 pinctrl_salt9_default: salt9_default {
1745 function = "SALT9";
1746 groups = "SALT9";
1747 };
1748
1749 pinctrl_scl1_default: scl1_default {
1750 function = "SCL1";
1751 groups = "SCL1";
1752 };
1753
1754 pinctrl_scl2_default: scl2_default {
1755 function = "SCL2";
1756 groups = "SCL2";
1757 };
1758
1759 pinctrl_sd1_default: sd1_default {
1760 function = "SD1";
1761 groups = "SD1";
1762 };
1763
1764 pinctrl_sd2_default: sd2_default {
1765 function = "SD2";
1766 groups = "SD2";
1767 };
1768
1769 pinctrl_emmc_default: emmc_default {
1770 function = "EMMC";
1771 groups = "EMMC";
1772 };
1773
1774 pinctrl_emmcg8_default: emmcg8_default {
1775 function = "EMMCG8";
1776 groups = "EMMCG8";
1777 };
1778
1779 pinctrl_sda1_default: sda1_default {
1780 function = "SDA1";
1781 groups = "SDA1";
1782 };
1783
1784 pinctrl_sda2_default: sda2_default {
1785 function = "SDA2";
1786 groups = "SDA2";
1787 };
1788
1789 pinctrl_sgps1_default: sgps1_default {
1790 function = "SGPS1";
1791 groups = "SGPS1";
1792 };
1793
1794 pinctrl_sgps2_default: sgps2_default {
1795 function = "SGPS2";
1796 groups = "SGPS2";
1797 };
1798
1799 pinctrl_sioonctrl_default: sioonctrl_default {
1800 function = "SIOONCTRL";
1801 groups = "SIOONCTRL";
1802 };
1803
1804 pinctrl_siopbi_default: siopbi_default {
1805 function = "SIOPBI";
1806 groups = "SIOPBI";
1807 };
1808
1809 pinctrl_siopbo_default: siopbo_default {
1810 function = "SIOPBO";
1811 groups = "SIOPBO";
1812 };
1813
1814 pinctrl_siopwreq_default: siopwreq_default {
1815 function = "SIOPWREQ";
1816 groups = "SIOPWREQ";
1817 };
1818
1819 pinctrl_siopwrgd_default: siopwrgd_default {
1820 function = "SIOPWRGD";
1821 groups = "SIOPWRGD";
1822 };
1823
1824 pinctrl_sios3_default: sios3_default {
1825 function = "SIOS3";
1826 groups = "SIOS3";
1827 };
1828
1829 pinctrl_sios5_default: sios5_default {
1830 function = "SIOS5";
1831 groups = "SIOS5";
1832 };
1833
1834 pinctrl_siosci_default: siosci_default {
1835 function = "SIOSCI";
1836 groups = "SIOSCI";
1837 };
1838
1839 pinctrl_spi1_default: spi1_default {
1840 function = "SPI1";
1841 groups = "SPI1";
1842 };
1843
1844 pinctrl_spi1cs1_default: spi1cs1_default {
1845 function = "SPI1CS1";
1846 groups = "SPI1CS1";
1847 };
1848
1849 pinctrl_spi1debug_default: spi1debug_default {
1850 function = "SPI1DEBUG";
1851 groups = "SPI1DEBUG";
1852 };
1853
1854 pinctrl_spi1passthru_default: spi1passthru_default {
1855 function = "SPI1PASSTHRU";
1856 groups = "SPI1PASSTHRU";
1857 };
1858
1859 pinctrl_spi2ck_default: spi2ck_default {
1860 function = "SPI2CK";
1861 groups = "SPI2CK";
1862 };
1863
1864 pinctrl_spi2cs0_default: spi2cs0_default {
1865 function = "SPI2CS0";
1866 groups = "SPI2CS0";
1867 };
1868
1869 pinctrl_spi2cs1_default: spi2cs1_default {
1870 function = "SPI2CS1";
1871 groups = "SPI2CS1";
1872 };
1873
1874 pinctrl_spi2miso_default: spi2miso_default {
1875 function = "SPI2MISO";
1876 groups = "SPI2MISO";
1877 };
1878
1879 pinctrl_spi2mosi_default: spi2mosi_default {
1880 function = "SPI2MOSI";
1881 groups = "SPI2MOSI";
1882 };
1883
1884 pinctrl_timer3_default: timer3_default {
1885 function = "TIMER3";
1886 groups = "TIMER3";
1887 };
1888
1889 pinctrl_timer4_default: timer4_default {
1890 function = "TIMER4";
1891 groups = "TIMER4";
1892 };
1893
1894 pinctrl_timer5_default: timer5_default {
1895 function = "TIMER5";
1896 groups = "TIMER5";
1897 };
1898
1899 pinctrl_timer6_default: timer6_default {
1900 function = "TIMER6";
1901 groups = "TIMER6";
1902 };
1903
1904 pinctrl_timer7_default: timer7_default {
1905 function = "TIMER7";
1906 groups = "TIMER7";
1907 };
1908
1909 pinctrl_timer8_default: timer8_default {
1910 function = "TIMER8";
1911 groups = "TIMER8";
1912 };
1913
1914 pinctrl_txd1_default: txd1_default {
1915 function = "TXD1";
1916 groups = "TXD1";
1917 };
1918
1919 pinctrl_txd2_default: txd2_default {
1920 function = "TXD2";
1921 groups = "TXD2";
1922 };
1923
1924 pinctrl_txd3_default: txd3_default {
1925 function = "TXD3";
1926 groups = "TXD3";
1927 };
1928
1929 pinctrl_txd4_default: txd4_default {
1930 function = "TXD4";
1931 groups = "TXD4";
1932 };
1933
1934 pinctrl_uart6_default: uart6_default {
1935 function = "UART6";
1936 groups = "UART6";
1937 };
1938
1939 pinctrl_usbcki_default: usbcki_default {
1940 function = "USBCKI";
1941 groups = "USBCKI";
1942 };
1943
1944 pinctrl_usb2ah_default: usb2ah_default {
1945 function = "USB2AH";
1946 groups = "USB2AH";
1947 };
1948
1949 pinctrl_usb11bhid_default: usb11bhid_default {
1950 function = "USB11BHID";
1951 groups = "USB11BHID";
1952 };
1953
1954 pinctrl_usb2bh_default: usb2bh_default {
1955 function = "USB2BH";
1956 groups = "USB2BH";
1957 };
1958
1959 pinctrl_vgabiosrom_default: vgabiosrom_default {
1960 function = "VGABIOSROM";
1961 groups = "VGABIOSROM";
1962 };
1963
1964 pinctrl_vgahs_default: vgahs_default {
1965 function = "VGAHS";
1966 groups = "VGAHS";
1967 };
1968
1969 pinctrl_vgavs_default: vgavs_default {
1970 function = "VGAVS";
1971 groups = "VGAVS";
1972 };
1973
1974 pinctrl_vpi24_default: vpi24_default {
1975 function = "VPI24";
1976 groups = "VPI24";
1977 };
1978
1979 pinctrl_vpo_default: vpo_default {
1980 function = "VPO";
1981 groups = "VPO";
1982 };
1983
1984 pinctrl_wdtrst1_default: wdtrst1_default {
1985 function = "WDTRST1";
1986 groups = "WDTRST1";
1987 };
1988
1989 pinctrl_wdtrst2_default: wdtrst2_default {
1990 function = "WDTRST2";
1991 groups = "WDTRST2";
1992 };
1993
1994 pinctrl_pcie0rc_default: pcie0rc_default {
1995 function = "PCIE0RC";
1996 groups = "PCIE0RC";
1997 };
1998
1999 pinctrl_pcie1rc_default: pcie1rc_default {
2000 function = "PCIE1RC";
2001 groups = "PCIE1RC";
2002 };
2003};