| Graeme Russ | 6506c25 | 2008-11-22 08:43:29 +1100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef _ASM_IC_SC520_PCI_H_ |
| 25 | #define _ASM_IC_SC520_PCI_H_ 1 |
| 26 | |
| Graeme Russ | 5514035 | 2010-04-24 00:05:53 +1000 | [diff] [blame] | 27 | /* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ |
| 28 | #define SC520_REG_ADDR 0x00000cf8 |
| 29 | #define SC520_REG_DATA 0x00000cfc |
| 30 | |
| 31 | #define SC520_ISA_MEM_PHYS 0x00000000 |
| 32 | #define SC520_ISA_MEM_BUS 0x00000000 |
| 33 | #define SC520_ISA_MEM_SIZE 0x01000000 |
| 34 | |
| 35 | #define SC520_ISA_IO_PHYS 0x00000000 |
| 36 | #define SC520_ISA_IO_BUS 0x00000000 |
| 37 | #define SC520_ISA_IO_SIZE 0x00001000 |
| 38 | |
| 39 | /* PCI I/O space from 0x1000 to 0xdfff |
| 40 | * (make 0xe000-0xfdff available for stuff like PCCard boot) */ |
| 41 | #define SC520_PCI_IO_PHYS 0x00001000 |
| 42 | #define SC520_PCI_IO_BUS 0x00001000 |
| 43 | #define SC520_PCI_IO_SIZE 0x0000d000 |
| 44 | |
| 45 | /* system memory from 0x00000000 to 0x0fffffff */ |
| 46 | #define SC520_PCI_MEMORY_PHYS 0x00000000 |
| 47 | #define SC520_PCI_MEMORY_BUS 0x00000000 |
| 48 | #define SC520_PCI_MEMORY_SIZE 0x10000000 |
| 49 | |
| 50 | /* PCI bus memory from 0x10000000 to 0x26ffffff |
| 51 | * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ |
| 52 | #define SC520_PCI_MEM_PHYS 0x10000000 |
| 53 | #define SC520_PCI_MEM_BUS 0x10000000 |
| 54 | #define SC520_PCI_MEM_SIZE 0x17000000 |
| 55 | |
| Graeme Russ | 6506c25 | 2008-11-22 08:43:29 +1100 | [diff] [blame] | 56 | /* pin number used for PCI interrupt mappings */ |
| 57 | #define SC520_PCI_INTA 0 |
| 58 | #define SC520_PCI_INTB 1 |
| 59 | #define SC520_PCI_INTC 2 |
| 60 | #define SC520_PCI_INTD 3 |
| 61 | #define SC520_PCI_GPIRQ0 4 |
| 62 | #define SC520_PCI_GPIRQ1 5 |
| 63 | #define SC520_PCI_GPIRQ2 6 |
| 64 | #define SC520_PCI_GPIRQ3 7 |
| 65 | #define SC520_PCI_GPIRQ4 8 |
| 66 | #define SC520_PCI_GPIRQ5 9 |
| 67 | #define SC520_PCI_GPIRQ6 10 |
| 68 | #define SC520_PCI_GPIRQ7 11 |
| 69 | #define SC520_PCI_GPIRQ8 12 |
| 70 | #define SC520_PCI_GPIRQ9 13 |
| 71 | #define SC520_PCI_GPIRQ10 14 |
| 72 | |
| 73 | extern int sc520_pci_ints[]; |
| 74 | |
| 75 | void pci_sc520_init(struct pci_controller *hose); |
| Graeme Russ | 6a55457 | 2010-04-24 00:05:54 +1000 | [diff] [blame] | 76 | int pci_set_regions(struct pci_controller *hose); |
| Graeme Russ | 6506c25 | 2008-11-22 08:43:29 +1100 | [diff] [blame] | 77 | int pci_sc520_set_irq(int pci_pin, int irq); |
| 78 | |
| 79 | #endif |