Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 3d1ebf7454cf51f34b1e29abc357caa976810a4b / . / arch / arm / mach-at91 / arm926ejs / at91sam9n12_devices.c
blob: 39f17a1e11e04c078ab44033f88a07f0b802231b [file] [log] [blame]
Wu, Josh3f338c12013-04-16 23:42:44 +0000[diff] [blame]1/*
2 * (C) Copyright 2013 Atmel Corporation
3 * Josh Wu <josh.wu@atmel.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Wu, Josh3f338c12013-04-16 23:42:44 +0000[diff] [blame]6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/at91_common.h>
11#include <asm/arch/at91_pmc.h>
12#include <asm/arch/at91_pio.h>
13
14unsigned int has_lcdc()
15{
16 return 1;
17}
18
19void at91_serial0_hw_init(void)
20{
21 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
22
23 at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
24 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
25 writel(1 << ATMEL_ID_USART0, &pmc->pcer);
26}
27
28void at91_serial1_hw_init(void)
29{
30 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
31
32 at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
33 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
34 writel(1 << ATMEL_ID_USART1, &pmc->pcer);
35}
36
37void at91_serial2_hw_init(void)
38{
39 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
40
41 at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
42 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
43 writel(1 << ATMEL_ID_USART2, &pmc->pcer);
44}
45
46void at91_serial3_hw_init(void)
47{
48 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
49
50 at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
51 at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
52 writel(1 << ATMEL_ID_USART3, &pmc->pcer);
53}
54
55void at91_seriald_hw_init(void)
56{
57 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
58
59 at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
60 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
61 writel(1 << ATMEL_ID_SYS, &pmc->pcer);
62}
63
64#ifdef CONFIG_ATMEL_SPI
65void at91_spi0_hw_init(unsigned long cs_mask)
66{
67 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
68
69 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
70 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
71 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
72
73 /* Enable clock */
74 writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
75
76 if (cs_mask & (1 << 0))
77 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
78 if (cs_mask & (1 << 1))
79 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
80 if (cs_mask & (1 << 2))
81 at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
82 if (cs_mask & (1 << 3))
83 at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
84}
85
86void at91_spi1_hw_init(unsigned long cs_mask)
87{
88 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
89
90 at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
91 at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
92 at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
93
94 /* Enable clock */
95 writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
96
97 if (cs_mask & (1 << 0))
98 at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
99 if (cs_mask & (1 << 1))
100 at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
101 if (cs_mask & (1 << 2))
102 at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
103 if (cs_mask & (1 << 3))
104 at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
105}
106#endif
107
108void at91_mci_hw_init(void)
109{
110 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
111
112 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
113 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
114 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
115 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
116 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
117 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
118
119 writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
120}
121
122#ifdef CONFIG_LCD
123void at91_lcd_hw_init(void)
124{
125 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
126
127 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
128 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
129 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
130 at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
131 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
132 at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
133
134 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
135 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
136 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
137 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
138 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
139 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
140 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
141 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
142 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
143 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
144 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
145 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
146 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
147 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
148 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
149 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
150 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
151 at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
152 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
153 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
154 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
155 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
156 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
157 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
158
159 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
160}
161#endif