Blame - arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds - filogic/uboot

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Tom Rini	10e4779	2018-05-06 17:58:06 -0400	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	2	/*
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	3	* Copyright (C) 2015 Stefan Roese <sr@denx.de>
				4	*
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	5	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
				6	* on behalf of DENX Software Engineering GmbH
				7	*
				8	* January 2004 - Changed to support H4 device
				9	* Copyright (c) 2004-2008 Texas Instruments
				10	*
				11	* (C) Copyright 2002
				12	* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	13	*/
				14
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	15	MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
				16	LENGTH = CONFIG_SPL_MAX_SIZE }
				17
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	18	OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
				19	OUTPUT_ARCH(arm)
				20	ENTRY(_start)
				21	SECTIONS
				22	{
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	23	.text :
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	24	{
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	25	__start = .;
Albert ARIBAUD	9852cc6	2014-04-15 16:13:51 +0200	[diff] [blame]	26	*(.vectors)
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	27	CPUDIR/spear/start.o (.text*)
Benoît Thébaudeau	3954db8	2013-04-11 09:36:03 +0000	[diff] [blame]	28	(.text)
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	29	} > .sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	30
				31	. = ALIGN(4);
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	32	.rodata : { (SORT_BY_ALIGNMENT(.rodata)) } >.sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	33
				34	. = ALIGN(4);
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	35	.data : { (SORT_BY_ALIGNMENT(.data)) } >.sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	36
				37	. = ALIGN(4);
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	38	.u_boot_list : {
				39	KEEP((SORT(.u_boot_list)));
				40	} > .sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	41
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	42	. = ALIGN(4);
				43	__image_copy_end = .;
				44	_end = .;
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	45
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	46	.bss :
				47	{
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	48	. = ALIGN(4);
				49	__bss_start = .;
				50	(.bss)
				51	. = ALIGN(4);
Simon Glass	ed70c8f	2013-03-14 06:54:53 +0000	[diff] [blame]	52	__bss_end = .;
Stefan Roese	7618ad0	2015-08-18 09:27:17 +0200	[diff] [blame]	53	} > .sram
Stefan Roese	c6bc1db	2012-01-03 16:49:01 +0100	[diff] [blame]	54	}