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Poonam Aggrwalf857ed92009-08-21 07:29:58 +05301/*
Kumar Galad0f27d32010-07-08 22:37:44 -05002 * Copyright 2009-2010 Freescale Semiconductor, Inc.
Poonam Aggrwalf857ed92009-08-21 07:29:58 +05303 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/immap_85xx.h>
Kumar Gala3d020382010-12-15 04:55:20 -060027#include <asm/fsl_serdes.h>
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053028#include <asm/io.h>
29#include <asm/fsl_pci.h>
30#include <libfdt.h>
31#include <fdt_support.h>
32
33DECLARE_GLOBAL_DATA_PTR;
34
35#ifdef CONFIG_PCIE1
36static struct pci_controller pcie1_hose;
37#endif
38
39#ifdef CONFIG_PCIE2
40static struct pci_controller pcie2_hose;
41#endif
42
43void pci_init_board(void)
44{
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053045 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala584fae52009-09-03 10:09:04 -050046 struct fsl_pci_info pci_info[2];
Kumar Gala3d020382010-12-15 04:55:20 -060047 u32 devdisr, pordevsr;
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053048 int first_free_busno = 0;
Kumar Gala584fae52009-09-03 10:09:04 -050049 int num = 0;
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053050
51 int pcie_ep, pcie_configured;
52
Kumar Gala584fae52009-09-03 10:09:04 -050053 devdisr = in_be32(&gur->devdisr);
54 pordevsr = in_be32(&gur->pordevsr);
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053055
Kumar Gala584fae52009-09-03 10:09:04 -050056 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
Peter Tyser8e9134c2010-10-29 17:59:25 -050057 printf("eTSEC2 is in sgmii mode.\n");
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053058
Kumar Gala584fae52009-09-03 10:09:04 -050059 puts("\n");
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053060#ifdef CONFIG_PCIE2
Kumar Gala3d020382010-12-15 04:55:20 -060061 pcie_configured = is_serdes_configured(PCIE2);
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053062
63 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
Kumar Gala584fae52009-09-03 10:09:04 -050064 SET_STD_PCIE_INFO(pci_info[num], 2);
Kumar Gala5a0b9bd2009-11-04 13:01:38 -060065 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
Peter Tyser2b91f712010-10-29 17:59:24 -050066 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
67 pcie_ep ? "Endpoint" : "Root Complex",
68 pci_info[num].regs);
Kumar Gala584fae52009-09-03 10:09:04 -050069 first_free_busno = fsl_pci_init_port(&pci_info[num++],
Kumar Galab83ff072009-11-04 01:29:04 -060070 &pcie2_hose, first_free_busno);
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053071 } else {
Peter Tyser2b91f712010-10-29 17:59:24 -050072 printf("PCIE2: disabled\n");
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053073 }
Kumar Gala584fae52009-09-03 10:09:04 -050074 puts("\n");
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053075#else
Kumar Gala584fae52009-09-03 10:09:04 -050076 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053077#endif
78
79#ifdef CONFIG_PCIE1
Kumar Gala3d020382010-12-15 04:55:20 -060080 pcie_configured = is_serdes_configured(PCIE1);
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053081
82 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
Kumar Gala584fae52009-09-03 10:09:04 -050083 SET_STD_PCIE_INFO(pci_info[num], 1);
Kumar Gala5a0b9bd2009-11-04 13:01:38 -060084 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
Peter Tyser2b91f712010-10-29 17:59:24 -050085 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
86 pcie_ep ? "Endpoint" : "Root Complex",
87 pci_info[num].regs);
Kumar Gala584fae52009-09-03 10:09:04 -050088 first_free_busno = fsl_pci_init_port(&pci_info[num++],
Kumar Galab83ff072009-11-04 01:29:04 -060089 &pcie1_hose, first_free_busno);
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053090 } else {
Peter Tyser2b91f712010-10-29 17:59:24 -050091 printf("PCIE1: disabled\n");
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053092 }
Kumar Gala584fae52009-09-03 10:09:04 -050093 puts("\n");
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053094#else
Kumar Gala584fae52009-09-03 10:09:04 -050095 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053096#endif
97}
98
99void ft_pci_board_setup(void *blob)
100{
Kumar Galad0f27d32010-07-08 22:37:44 -0500101 FT_FSL_PCI_SETUP;
Poonam Aggrwalf857ed92009-08-21 07:29:58 +0530102}