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git01.mediatek.com / filogic / uboot / 3cd07dce6576f2a06fed1303722b3347ba2f232c / . / arch / arm / include / asm / arch-am33xx / hardware.h
blob: 02f5f8a8d25903984e4d620cc7bdd58adc9ccd9e [file] [log] [blame]
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]1/*
2 * hardware.h
3 *
4 * hardware specific header
5 *
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]9 */
10
11#ifndef __AM33XX_HARDWARE_H
12#define __AM33XX_HARDWARE_H
13
Matt Porter691fbe32013-03-15 10:07:06 +0000[diff] [blame]14#include <config.h>
Tom Riniee5bce42012-08-08 17:03:10 -0700[diff] [blame]15#include <asm/arch/omap.h>
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]16#ifdef CONFIG_AM33XX
17#include <asm/arch/hardware_am33xx.h>
18#elif defined(CONFIG_TI814X)
19#include <asm/arch/hardware_ti814x.h>
20#endif
Tom Riniee5bce42012-08-08 17:03:10 -0700[diff] [blame]21
Matt Porter691fbe32013-03-15 10:07:06 +0000[diff] [blame]22/*
23 * Common hardware definitions
24 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]25
26/* DM Timer base addresses */
27#define DM_TIMER0_BASE 0x4802C000
28#define DM_TIMER1_BASE 0x4802E000
29#define DM_TIMER2_BASE 0x48040000
30#define DM_TIMER3_BASE 0x48042000
31#define DM_TIMER4_BASE 0x48044000
32#define DM_TIMER5_BASE 0x48046000
33#define DM_TIMER6_BASE 0x48048000
34#define DM_TIMER7_BASE 0x4804A000
35
36/* GPIO Base address */
37#define GPIO0_BASE 0x48032000
38#define GPIO1_BASE 0x4804C000
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]39
40/* BCH Error Location Module */
41#define ELM_BASE 0x48080000
42
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]43/* EMIF Base address */
44#define EMIF4_0_CFG_BASE 0x4C000000
45#define EMIF4_1_CFG_BASE 0x4D000000
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]46
47/* PLL related registers */
48#define CM_PER 0x44E00000
49#define CM_WKUP 0x44E00400
50#define CM_DPLL 0x44E00500
51#define CM_DEVICE 0x44E00700
Vaibhav Hiremath2d7da5f2012-03-08 17:15:47 +0530[diff] [blame]52#define CM_RTC 0x44E00800
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]53#define CM_CEFUSE 0x44E00A00
54#define PRM_DEVICE 0x44E00F00
55
56/* VTP Base address */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]57#define VTP1_CTRL_ADDR 0x48140E10
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]58
59/* DDR Base address */
60#define DDR_CTRL_ADDR 0x44E10E04
61#define DDR_CONTROL_BASE_ADDR 0x44E11404
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]62#define DDR_PHY_CMD_ADDR2 0x47C0C800
63#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]64
65/* UART */
66#define DEFAULT_UART_BASE UART0_BASE
67
68#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
69#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
70
Ilya Yanok2ebbb862012-11-06 13:06:30 +0000[diff] [blame]71/* GPMC Base address */
72#define GPMC_BASE 0x50000000
73
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]74/* CPSW Config space */
Matt Portere24646f2013-03-15 10:07:02 +0000[diff] [blame]75#define CPSW_BASE 0x4A100000
Vaibhav Hiremath2d7da5f2012-03-08 17:15:47 +0530[diff] [blame]76
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]77/* OTG */
Matt Portere24646f2013-03-15 10:07:02 +0000[diff] [blame]78#define USB0_OTG_BASE 0x47401000
79#define USB1_OTG_BASE 0x47401800
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]80
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]81#endif /* __AM33XX_HARDWARE_H */