Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 3 | * Copyright 2018, 2020 NXP |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/arch/fsl_serdes.h> |
| 8 | |
| 9 | struct serdes_config { |
| 10 | u8 protocol; |
| 11 | u8 lanes[SRDS_MAX_LANES]; |
| 12 | }; |
| 13 | |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 14 | #if defined(CONFIG_ARCH_LX2162A) |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 15 | static struct serdes_config serdes1_cfg_tbl[] = { |
| 16 | /* SerDes 1 */ |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 17 | {0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } }, |
| 18 | {0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } }, |
| 19 | {0x03, {XFI6, XFI5, XFI4, XFI3 } }, |
| 20 | {0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } }, |
| 21 | {0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } }, |
| 22 | {0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } }, |
| 23 | {0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } }, |
| 24 | {0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } }, |
| 25 | {0x12, {_25GE6, _25GE5, XFI4, XFI3 } }, |
| 26 | {0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } }, |
| 27 | {} |
| 28 | }; |
| 29 | #else |
| 30 | static struct serdes_config serdes1_cfg_tbl[] = { |
| 31 | /* SerDes 1 */ |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 32 | {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, |
| 33 | {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, |
| 34 | {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, |
| 35 | XFI3 } }, |
| 36 | {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, |
| 37 | SGMII3 } }, |
| 38 | {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, |
| 39 | PCIE1 } }, |
| 40 | {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, |
| 41 | XFI3 } }, |
| 42 | {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, |
| 43 | XFI3 } }, |
| 44 | {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, |
| 45 | {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, |
| 46 | PCIE1 } }, |
| 47 | {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, |
| 48 | {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, |
| 49 | {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, |
| 50 | {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, |
| 51 | _100GE1 } }, |
| 52 | {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, |
| 53 | _100GE1 } }, |
| 54 | {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, |
| 55 | {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, |
| 56 | {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, |
| 57 | {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, |
| 58 | XFI3 } }, |
| 59 | {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, |
| 60 | {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, |
| 61 | _40GE1 } }, |
| 62 | {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, |
| 63 | _25GE3 } }, |
| 64 | {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, |
| 65 | {} |
| 66 | }; |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 67 | #endif |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 68 | |
| 69 | static struct serdes_config serdes2_cfg_tbl[] = { |
| 70 | /* SerDes 2 */ |
| 71 | {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, |
| 72 | {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, |
| 73 | {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, |
| 74 | {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, |
| 75 | {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, |
| 76 | {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, |
| 77 | XFI14 } }, |
| 78 | {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, |
| 79 | XFI14 } }, |
| 80 | {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, |
| 81 | {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, |
| 82 | SGMII14} }, |
| 83 | {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, |
| 84 | PCIE4 } }, |
| 85 | {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, |
| 86 | SGMII14 } }, |
| 87 | {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, |
| 88 | SATA2 } }, |
| 89 | {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, |
| 90 | {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, |
| 91 | SGMII14 } }, |
| 92 | {} |
| 93 | }; |
| 94 | |
| 95 | static struct serdes_config serdes3_cfg_tbl[] = { |
| 96 | /* SerDes 3 */ |
| 97 | {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, |
| 98 | {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, |
| 99 | {} |
| 100 | }; |
| 101 | |
| 102 | static struct serdes_config *serdes_cfg_tbl[] = { |
| 103 | serdes1_cfg_tbl, |
| 104 | serdes2_cfg_tbl, |
| 105 | serdes3_cfg_tbl, |
| 106 | }; |
| 107 | |
| 108 | enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) |
| 109 | { |
| 110 | struct serdes_config *ptr; |
| 111 | |
| 112 | if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
| 113 | return 0; |
| 114 | |
| 115 | ptr = serdes_cfg_tbl[serdes]; |
| 116 | while (ptr->protocol) { |
| 117 | if (ptr->protocol == cfg) |
| 118 | return ptr->lanes[lane]; |
| 119 | ptr++; |
| 120 | } |
| 121 | |
| 122 | return 0; |
| 123 | } |
| 124 | |
| 125 | int is_serdes_prtcl_valid(int serdes, u32 prtcl) |
| 126 | { |
| 127 | int i; |
| 128 | struct serdes_config *ptr; |
| 129 | |
| 130 | if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
| 131 | return 0; |
| 132 | |
| 133 | ptr = serdes_cfg_tbl[serdes]; |
| 134 | while (ptr->protocol) { |
| 135 | if (ptr->protocol == prtcl) |
| 136 | break; |
| 137 | ptr++; |
| 138 | } |
| 139 | |
| 140 | if (!ptr->protocol) |
| 141 | return 0; |
| 142 | |
| 143 | for (i = 0; i < SRDS_MAX_LANES; i++) { |
| 144 | if (ptr->lanes[i] != NONE) |
| 145 | return 1; |
| 146 | } |
| 147 | |
| 148 | return 0; |
| 149 | } |