blob: e9947ea492380be0326efd971fa129baac4e3c4d [file] [log] [blame]
Joseph Chen72cd8792021-06-02 15:58:25 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3568_COMMON_H
7#define __CONFIG_RK3568_COMMON_H
8
9#include "rockchip-common.h"
10
11#define CONFIG_SYS_CBSIZE 1024
Joseph Chen72cd8792021-06-02 15:58:25 +080012
Joseph Chen72cd8792021-06-02 15:58:25 +080013#define CONFIG_IRAM_BASE 0xfdcc0000
14
15#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
Nico Cheng00ceeb02021-10-26 10:42:19 +080016
17#define CONFIG_SPL_STACK 0x00400000
18#define CONFIG_SPL_MAX_SIZE 0x20000
19#define CONFIG_SPL_BSS_START_ADDR 0x4000000
20#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
21
Joseph Chen72cd8792021-06-02 15:58:25 +080022#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
23
24#define CONFIG_SYS_SDRAM_BASE 0
25#define SDRAM_MAX_SIZE 0xf0000000
26
27#ifndef CONFIG_SPL_BUILD
28#define ENV_MEM_LAYOUT_SETTINGS \
29 "scriptaddr=0x00c00000\0" \
30 "pxefile_addr_r=0x00e00000\0" \
31 "fdt_addr_r=0x0a100000\0" \
32 "kernel_addr_r=0x02080000\0" \
33 "ramdisk_addr_r=0x0a200000\0"
34
35#include <config_distro_bootcmd.h>
36#define CONFIG_EXTRA_ENV_SETTINGS \
37 ENV_MEM_LAYOUT_SETTINGS \
38 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
39 "partitions=" PARTS_DEFAULT \
40 ROCKCHIP_DEVICE_SETTINGS \
41 BOOTENV
42#endif
43
44#endif