| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor |
| Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __CPLD_H__ |
| 7 | #define __CPLD_H__ |
| 8 | |
| 9 | /* |
| 10 | * CPLD register set of LS1043ARDB board-specific. |
| 11 | */ |
| 12 | struct cpld_data { |
| 13 | u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ |
| 14 | u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ |
| 15 | u8 pcba_ver; /* 0x2 - PCBA Revision Register */ |
| 16 | u8 system_rst; /* 0x3 - system reset register */ |
| 17 | u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ |
| 18 | u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */ |
| 19 | u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */ |
| 20 | u8 vbank; /* 0x7 - Flash bank selection Control */ |
| 21 | u8 sysclk_sel; /* 0x8 - */ |
| 22 | u8 uart_sel; /* 0x9 - */ |
| 23 | u8 sd1refclk_sel; /* 0xA - */ |
| 24 | u8 tdmclk_mux_sel; /* 0xB - */ |
| 25 | u8 sdhc_spics_sel; /* 0xC - */ |
| 26 | u8 status_led; /* 0xD - */ |
| 27 | u8 global_rst; /* 0xE - */ |
| 28 | }; |
| 29 | |
| 30 | u8 cpld_read(unsigned int reg); |
| 31 | void cpld_write(unsigned int reg, u8 value); |
| 32 | void cpld_rev_bit(unsigned char *value); |
| 33 | |
| 34 | #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) |
| 35 | #define CPLD_WRITE(reg, value) \ |
| 36 | cpld_write(offsetof(struct cpld_data, reg), value) |
| 37 | |
| 38 | /* CPLD on IFC */ |
| 39 | #define CPLD_SW_MUX_BANK_SEL 0x40 |
| 40 | #define CPLD_BANK_SEL_MASK 0x07 |
| 41 | #define CPLD_BANK_SEL_ALTBANK 0x04 |
| Qianyu Gong | 24be17c | 2016-04-25 16:38:35 +0800 | [diff] [blame] | 42 | #define CPLD_CFG_RCW_SRC_NOR 0x025 |
| Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 43 | #define CPLD_CFG_RCW_SRC_NAND 0x106 |
| Wei Lu | 795e806 | 2022-09-26 16:18:49 +0800 | [diff] [blame] | 44 | #define CPLD_CFG_RCW_SRC_NAND_4K 0x118 |
| Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 45 | #define CPLD_CFG_RCW_SRC_SD 0x040 |
| Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 46 | #endif |