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Sandeep Paulraj3c86e5e2010-12-28 15:43:16 -05001/*
2 * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <common.h>
22#include <net.h>
23#include <miiphy.h>
24#include <asm/arch/emac_defs.h>
25
26#ifdef CONFIG_DRIVER_TI_EMAC
27
28#ifdef CONFIG_CMD_NET
29
30/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
31
32#define MII_PHY_CONFIG_REG 22
33
34/* PHY Config bits */
35#define PHY_SYS_CLK_EN (1 << 4)
36
37int et1011c_get_link_speed(int phy_addr)
38{
39 u_int16_t data;
40
41 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
42 davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
43 MII_PHY_CONFIG_REG, &data);
44 /* Enable 125MHz clock sourced from PHY */
45 davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
46 MII_PHY_CONFIG_REG,
47 data | PHY_SYS_CLK_EN);
48 return (1);
49 }
50 return (0);
51}
52
53#endif /* CONFIG_CMD_NET */
54
55#endif /* CONFIG_DRIVER_ETHER */